Searched refs:ISR_RX_FIFO_FULL (Results 1 – 2 of 2) sorted by relevance
52 ISR_RX_FIFO_FULL = BIT(3), /* Receive FIFO Full */ enumerator
54 (ISR_ADDR_TARGET | ISR_NOT_ADDR_TARGET | ISR_RX_FIFO_FULL | ISR_TX_FIFO_EMPTY | \161 *int_enable |= ISR_RX_FIFO_FULL; in i2c_xilinx_axi_target_isr()182 } else if (data->target_writing && (*int_status & ISR_RX_FIFO_FULL)) { in i2c_xilinx_axi_target_isr()183 *int_status &= ~ISR_RX_FIFO_FULL; in i2c_xilinx_axi_target_isr()303 i2c_xilinx_axi_clear_interrupt(config, data, ISR_RX_FIFO_FULL); in i2c_xilinx_axi_wait_rx_full()311 events = i2c_xilinx_axi_wait_interrupt(config, data, ISR_RX_FIFO_FULL | ISR_ARB_LOST); in i2c_xilinx_axi_wait_rx_full()
