Searched refs:INTR (Results 1 – 4 of 4) sorted by relevance
| /Zephyr-latest/arch/x86/core/intel64/ |
| D | locore.S | 895 #define INTR 0x8e macro
898 #define TRAP INTR
951 IDT(Z_X86_OOPS_VECTOR, USER_INTR, EXC_STACK); IDT( 33, INTR, IRQ_STACK)
952 IDT( 34, INTR, IRQ_STACK); IDT( 35, INTR, IRQ_STACK)
953 IDT( 36, INTR, IRQ_STACK); IDT( 37, INTR, IRQ_STACK)
954 IDT( 38, INTR, IRQ_STACK); IDT( 39, INTR, IRQ_STACK)
955 IDT( 40, INTR, IRQ_STACK); IDT( 41, INTR, IRQ_STACK)
956 IDT( 42, INTR, IRQ_STACK); IDT( 43, INTR, IRQ_STACK)
957 IDT( 44, INTR, IRQ_STACK); IDT( 45, INTR, IRQ_STACK)
958 IDT( 46, INTR, IRQ_STACK); IDT( 47, INTR, IRQ_STACK)
[all …]
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_wch_rcc.c | 137 RCC->INTR = RCC_CSSC | RCC_PLLRDYC | RCC_HSERDYC | RCC_LSIRDYC; in clock_control_wch_rcc_init()
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.loapic | 22 interrupt for which the processor INTR signal is currently being
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| /Zephyr-latest/doc/releases/ |
| D | release-notes-2.7.rst | 1753 * :github:`35581` - stm32 SPI problems with DMA and INTR set-up
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