Searched refs:INTC (Results 1 – 8 of 8) sorted by relevance
| /Zephyr-latest/soc/mediatek/mt8xxx/ |
| D | soc.c | 101 #define INTC (*(volatile struct intc_8196 *)0x1a014000) macro
114 set_group_bit(&INTC.groups[i], irq, i == group); in mt8196_intc_set_irq_group()
122 INTC.enable = zero; in mt8196_intc_init()
123 INTC.polarity.lo = 0xffffffff; in mt8196_intc_init()
124 INTC.polarity.hi = 0xffffffff; in mt8196_intc_init()
125 INTC.wake_enable = zero; in mt8196_intc_init()
126 INTC.stage1_enable = zero; in mt8196_intc_init()
127 for (int i = 0; i < ARRAY_SIZE(INTC.groups); i++) { in mt8196_intc_init()
128 INTC.groups[i] = zero; in mt8196_intc_init()
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | Kconfig.xmc4xxx | 1 # XMC4XXX INTC configuration
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| D | Kconfig.nxp_irqsteer | 11 The IRQSTEER INTC provides support for MUX-ing
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| D | Kconfig | 59 module = INTC
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| /Zephyr-latest/boards/qemu/arc/doc/ |
| D | index.rst | 33 | ARCv2 INTC | on-chip | interrupt controller |
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| /Zephyr-latest/dts/arm/st/wb0/ |
| D | stm32wb0.dtsi | 144 * because that's where the GPIO INTC registers are located.
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| /Zephyr-latest/boards/ite/it82xx2_evb/doc/ |
| D | index.rst | 32 - GPIO, PWM, ADC, INTC, WUC, Timer, Watchdog, KB scan, JTAG
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| /Zephyr-latest/boards/others/neorv32/doc/ |
| D | index.rst | 31 | INTC | on-chip | interrupt controller |
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