1 /*
2  * Copyright (c) 2023 STMicroelectronics
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <zephyr/irq.h>
8 #include <zephyr/drivers/entropy.h>
9 #include <zephyr/logging/log.h>
10 #include <zephyr/drivers/clock_control.h>
11 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
12 
13 #include <stm32_ll_rng.h>
14 
15 #include "bleplat.h"
16 #include "bpka.h"
17 #include "linklayer_plat.h"
18 
19 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
20 LOG_MODULE_REGISTER(ble_plat);
21 
22 RAMCFG_HandleTypeDef hramcfg_SRAM1;
23 const struct device *rng_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_entropy));
24 
25 struct entropy_stm32_rng_dev_data {
26 	RNG_TypeDef *rng;
27 };
28 
29 struct entropy_stm32_rng_dev_cfg {
30 	struct stm32_pclken *pclken;
31 };
32 
BLEPLAT_Init(void)33 void BLEPLAT_Init(void)
34 {
35 	BPKA_Reset();
36 
37 	rng_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_entropy));
38 	if (!device_is_ready(rng_dev)) {
39 		LOG_ERR("error: random device not ready");
40 	}
41 }
42 
BLEPLAT_RngGet(uint8_t n,uint32_t * val)43 void BLEPLAT_RngGet(uint8_t n, uint32_t *val)
44 {
45 	LINKLAYER_PLAT_GetRNG((uint8_t *)val, 4 * n);
46 }
47 
BLEPLAT_PkaStartP256Key(const uint32_t * local_private_key)48 int BLEPLAT_PkaStartP256Key(const uint32_t *local_private_key)
49 {
50 	return BPKA_StartP256Key(local_private_key);
51 }
52 
BLEPLAT_PkaReadP256Key(uint32_t * local_public_key)53 void BLEPLAT_PkaReadP256Key(uint32_t *local_public_key)
54 {
55 	BPKA_ReadP256Key(local_public_key);
56 }
57 
BLEPLAT_PkaStartDhKey(const uint32_t * local_private_key,const uint32_t * remote_public_key)58 int BLEPLAT_PkaStartDhKey(const uint32_t *local_private_key,
59 			  const uint32_t *remote_public_key)
60 {
61 	return BPKA_StartDhKey(local_private_key, remote_public_key);
62 }
63 
BLEPLAT_PkaReadDhKey(uint32_t * dh_key)64 int BLEPLAT_PkaReadDhKey(uint32_t *dh_key)
65 {
66 	return BPKA_ReadDhKey(dh_key);
67 }
68 
BPKACB_Complete(void)69 void BPKACB_Complete(void)
70 {
71 	BLEPLATCB_PkaComplete();
72 }
73 
MX_RAMCFG_Init(void)74 void MX_RAMCFG_Init(void)
75 {
76 	/* Initialize RAMCFG SRAM1 */
77 	hramcfg_SRAM1.Instance = RAMCFG_SRAM1;
78 	if (HAL_RAMCFG_Init(&hramcfg_SRAM1) != HAL_OK) {
79 		LOG_ERR("Could not init RAMCFG");
80 	}
81 }
82 
Error_Handler(void)83 void Error_Handler(void)
84 {
85 	LOG_ERR("");
86 }
87 
enable_rng_clock(bool enable)88 void enable_rng_clock(bool enable)
89 {
90 	const struct entropy_stm32_rng_dev_cfg *dev_cfg = rng_dev->config;
91 	struct entropy_stm32_rng_dev_data *dev_data = rng_dev->data;
92 	struct stm32_pclken *rng_pclken;
93 	const struct device *rcc;
94 	unsigned int key;
95 
96 	rcc = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
97 	rng_pclken = (clock_control_subsys_t)&dev_cfg->pclken[0];
98 
99 	key = irq_lock();
100 
101 	/* Enable/Disable RNG clock only if not in use */
102 	if (!LL_RNG_IsEnabled((RNG_TypeDef *)dev_data->rng)) {
103 		if (enable) {
104 			clock_control_on(rcc, rng_pclken);
105 		} else {
106 			clock_control_off(rcc, rng_pclken);
107 		}
108 	}
109 
110 	irq_unlock(key);
111 }
112 
113 /* PKA IP requires RNG clock to be enabled
114  * These APIs are used by BLE controller to enable/disable RNG clock,
115  * based on PKA needs.
116  */
HW_RNG_DisableClock(uint8_t user_mask)117 void HW_RNG_DisableClock(uint8_t user_mask)
118 {
119 	ARG_UNUSED(user_mask);
120 
121 	enable_rng_clock(false);
122 }
123 
HW_RNG_EnableClock(uint8_t user_mask)124 void HW_RNG_EnableClock(uint8_t user_mask)
125 {
126 	ARG_UNUSED(user_mask);
127 
128 	enable_rng_clock(true);
129 }
130 
131 /* BLE ctlr should not disable HSI on its own */
SCM_HSI_CLK_OFF(void)132 void SCM_HSI_CLK_OFF(void) {}
133