Searched refs:GIRQ (Results 1 – 4 of 4) sorted by relevance
104 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_clr()116 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_SET = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_en()128 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_CLR = BIT(src_bit_pos); in mchp_xec_ecia_girq_src_dis()140 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].SRC = bitmap; in mchp_xec_ecia_girq_src_clr_bitmap()152 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_SET = bitmap; in mchp_xec_ecia_girq_src_en_bitmap()164 regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].EN_CLR = bitmap; in mchp_xec_ecia_girq_src_dis_bitmap()179 return regs->GIRQ[girq_num - MCHP_FIRST_GIRQ].RESULT; in mchp_xec_ecia_girq_result()260 regs->GIRQ[girq - MCHP_FIRST_GIRQ].EN_SET = BIT(src); in mchp_xec_ecia_enable()295 regs->GIRQ[girq - MCHP_FIRST_GIRQ].EN_CLR = BIT(src); in mchp_xec_ecia_disable()541 ecia->GIRQ[n].EN_CLR = UINT32_MAX; in xec_ecia_init()
49 int "XEX GIRQ Interrupt controller init priority"52 XEC GIRQ Interrupt controller device initialization priority.54 So that the XEC GIRQ controllers are initialized after the
118 ECIA_XEC_REGS->GIRQ[girq - 8].SRC = BIT(bitpos); in girq_src_clr()127 ECIA_XEC_REGS->GIRQ[girq - 8].EN_SET = BIT(bitpos); in girq_src_en()136 ECIA_XEC_REGS->GIRQ[girq - 8].EN_CLR = BIT(bitpos); in girq_src_dis()
1167 struct girq_regs GIRQ[19]; member1199 ecia->GIRQ[girq - 8u].SRC = BIT(pin); in mchp_soc_ecia_girq_src_clr()1211 ecia->GIRQ[girq - 8u].SRC = bitmap; in mchp_soc_ecia_girq_src_clr_bitmap()1223 ecia->GIRQ[girq - 8u].EN_CLR = BIT(pin); in mchp_soc_ecia_girq_src_dis()1235 ecia->GIRQ[girq - 8u].EN_SET = BIT(pin); in mchp_soc_ecia_girq_src_en()1246 return ecia->GIRQ[girq - 8u].RESULT; in mchp_soc_ecia_girq_result()
