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Searched refs:GICD_CTLR (Results 1 – 5 of 5) sorted by relevance

/Zephyr-latest/drivers/interrupt_controller/
Dintc_gicv3.c66 base = GICD_CTLR; in gic_wait_rwp()
456 if (sys_read32(GICD_CTLR) & (BIT(GICD_CTLR_ENABLE_G0) | BIT(GICD_CTLR_ENABLE_G1NS))) { in gicv3_dist_init()
466 sys_write32(0, GICD_CTLR); in gicv3_dist_init()
474 sys_set_bit(GICD_CTLR, GICD_CTRL_NS); in gicv3_dist_init()
475 __ASSERT(sys_test_bit(GICD_CTLR, GICD_CTRL_NS), in gicv3_dist_init()
515 GICD_CTLR); in gicv3_dist_init()
528 GICD_CTLR); in gicv3_dist_init()
531 sys_set_bit(GICD_CTLR, GICD_CTLR_ENABLE_G1S); in gicv3_dist_init()
Dintc_gic.c195 sys_write32(0, GICD_CTLR); in gic_dist_init()
244 sys_write32(1, GICD_CTLR); in gic_dist_init()
/Zephyr-latest/boards/arm/fvp_baser_aemv8r/
Dboard.cmake18 -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
52 -C gic_distributor.GICD_CTLR-DS-1-means-secure-only=1
/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dgic.h35 #define GICD_CTLR (GIC_DIST_BASE + 0x0) macro
/Zephyr-latest/boards/arm/fvp_baser_aemv8r/doc/
Ddebug-with-arm-ds.rst101 …c_ops=1 -C bp.refcounter.non_arch_start_at_default=1 -C gic_distributor.GICD_CTLR-DS-1-means-secur…