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Searched refs:GENMASK64 (Results 1 – 14 of 14) sorted by relevance

/Zephyr-latest/drivers/edac/
Dibecc.h13 #define BITFIELD64(val, h, l) (((val) & GENMASK64(h, l)) >> l)
62 #define TOUUD_MASK GENMASK64(38, 20)
70 #define TOM_MASK GENMASK64(38, 20)
76 #define MCHBAR_MASK GENMASK64(38, 16)
109 #define INJ_ADDR_BASE_MASK GENMASK64(38, 6)
112 #define INJ_ADDR_BASE_MASK_MASK GENMASK64(38, 6)
128 #define ECC_ERROR_ERRADD(val) ((val) & GENMASK64(38, 5))
/Zephyr-latest/subsys/fs/zms/
Dzms_priv.h21 #define ADDR_SECT_MASK GENMASK64(63, 32)
23 #define ADDR_OFFS_MASK GENMASK64(31, 0)
33 #define ZMS_LOOKUP_CACHE_NO_ADDR GENMASK64(63, 0)
/Zephyr-latest/drivers/flash/
Dflash_cadence_nand_ll.h264 #define ERASE_ADDR_SIZE (FIELD_PREP(GENMASK64(13, 11), 3ULL))
266 #define GEN_SECTOR_COUNT_SET (FIELD_PREP(GENMASK64(39, 32),\
269 #define GEN_LAST_SECTOR_SIZE_SET(x) (FIELD_PREP(GENMASK64(55, 40), x))
280 #define PAGE_MAX_BYTES(x) (FIELD_PREP(GENMASK64(13, 11), x))
286 #define GEN_SECTOR_SET(x) (FIELD_PREP(GENMASK64(31, 16), x))
287 #define PAGE_WRITE_10H_CMD (FIELD_PREP(GENMASK64(23, 16), 0x10ULL))
288 #define GEN_ADDR_WRITE_DATA(x) (FIELD_PREP(GENMASK64(63, 32), x))
/Zephyr-latest/drivers/dma/
Ddma_dw_axi.c92 #define DMA_DW_AXI_CFG_SRC_MULTBLK_TYPE(x) FIELD_PREP(GENMASK64(1, 0), x)
93 #define DMA_DW_AXI_CFG_DST_MULTBLK_TYPE(x) FIELD_PREP(GENMASK64(3, 2), x)
96 #define DMA_DW_AXI_CFG_SRC_PER(x) FIELD_PREP(GENMASK64(9, 4), x)
97 #define DMA_DW_AXI_CFG_DST_PER(x) FIELD_PREP(GENMASK64(16, 11), x)
100 #define DMA_DW_AXI_CFG_TT_FC(x) FIELD_PREP(GENMASK64(34, 32), x)
105 #define DMA_DW_AXI_CFG_PRIORITY(x) FIELD_PREP(GENMASK64(51, 47), x)
120 #define DMA_DW_AXI_CTL_ARLEN(x) FIELD_PREP(GENMASK64(46, 39), x)
124 #define DMA_DW_AXI_CTL_AWLEN(x) FIELD_PREP(GENMASK64(55, 48), x)
127 #define DMA_DW_AXI_CTL_SRC_MSIZE(x) FIELD_PREP(GENMASK64(17, 14), x)
129 #define DMA_DW_AXI_CTL_DST_MSIZE(x) FIELD_PREP(GENMASK64(21, 18), x)
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/Zephyr-latest/lib/libc/minimal/source/math/
Dsqrt.c16 #define EXP_MASK64 GENMASK64(62, 52)
/Zephyr-latest/include/zephyr/dsp/
Dprint_format.h46 #define __PRIq_arg_get(q, shift, h, l) FIELD_GET(GENMASK64(h, l), __PRIq_arg_shift(q, shift))
/Zephyr-latest/arch/arm64/core/
Dmmu.h127 #define PTE_PHYSADDR_MASK GENMASK64(47, PAGE_SIZE_SHIFT)
Dmmu.c188 uint64_t mask = DESC_ATTRS_MASK | GENMASK64(47, LEVEL_TO_VA_SIZE_SHIFT(level)); in is_desc_superset()
1160 *phys = par & GENMASK64(47, 12); in arch_page_phys_get()
/Zephyr-latest/subsys/sensing/sensor/phy_3d_sensor/
Dphy_3d_sensor.c35 FIELD_GET(GENMASK64(31 + shift, 31), shifted_value) * scale + in shifted_q31_to_scaled_int64()
36 (FIELD_GET(GENMASK64(30, 0), shifted_value) * scale / BIT(31)); in shifted_q31_to_scaled_int64()
/Zephyr-latest/subsys/secure_storage/src/its/store/
Dzms.c46 if (uid.uid & GENMASK64(63, ITS_CALLER_ID_POS)) { in has_forbidden_bits_set()
/Zephyr-latest/include/zephyr/drivers/
Dgpio.h456 (GENMASK64(DT_PROP_BY_IDX(node_id, prop, off_idx) + \
570 (GENMASK64(BITS_PER_LONG_LONG - 1, ngpios) \
663 ((GENMASK64(ngpios - 1, 0) & \
665 (GENMASK64(ngpios - 1, 0))) \
/Zephyr-latest/drivers/sensor/bosch/bmi160/
Demul_bmi160.c369 cfg->reg[reg_lsb] = FIELD_GET(GENMASK64(7, 0), intermediate); in bmi160_emul_backend_set_channel()
370 cfg->reg[reg_lsb + 1] = FIELD_GET(GENMASK64(15, 8), intermediate); in bmi160_emul_backend_set_channel()
/Zephyr-latest/include/zephyr/sys/
Dutil.h86 #define GENMASK64(h, l) \ macro
/Zephyr-latest/drivers/sensor/tdk/icm42688/
Dicm42688_decoder.c231 return FIELD_PREP(GENMASK(31, 22), whole) | (fraction * GENMASK64(21, 0) / 1000000); in icm42688_read_temperature_from_packet()