1 /*
2  * Copyright (c) 2022 YuLong Yao <feilongphone@gmail.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_
9 
10 #include "gd32-common.h"
11 
12 /**
13  * @name Register offsets
14  * @{
15  */
16 
17 #define GD32_AHBRST_OFFSET        0x28U
18 #define GD32_APB1RST_OFFSET       0x10U
19 #define GD32_APB2RST_OFFSET       0x0CU
20 
21 /** @} */
22 
23 /**
24  * @name Clock enable/disable definitions for peripherals
25  * @{
26  */
27 
28 
29 /* AHB peripherals */
30 #define GD32_RESET_DMA0     GD32_RESET_CONFIG(AHBRST, 0U)
31 #define GD32_RESET_DMA1     GD32_RESET_CONFIG(AHBRST, 1U)
32 #define GD32_RESET_SRAMSP   GD32_RESET_CONFIG(AHBRST, 2U)
33 #define GD32_RESET_DMAMUX   GD32_RESET_CONFIG(AHBRST, 3U)
34 #define GD32_RESET_FMCSP    GD32_RESET_CONFIG(AHBRST, 4U)
35 #define GD32_RESET_CRC      GD32_RESET_CONFIG(AHBRST, 6U)
36 #define GD32_RESET_MFCOM    GD32_RESET_CONFIG(AHBRST, 14U)
37 #define GD32_RESET_GPIOA    GD32_RESET_CONFIG(AHBRST, 17U)
38 #define GD32_RESET_GPIOB    GD32_RESET_CONFIG(AHBRST, 18U)
39 #define GD32_RESET_GPIOC    GD32_RESET_CONFIG(AHBRST, 19U)
40 #define GD32_RESET_GPIOD    GD32_RESET_CONFIG(AHBRST, 20U)
41 #define GD32_RESET_GPIOE    GD32_RESET_CONFIG(AHBRST, 21U)
42 #define GD32_RESET_GPIOF    GD32_RESET_CONFIG(AHBRST, 22U)
43 
44 /* APB1 peripherals */
45 #define GD32_RESET_TIMER1     GD32_RESET_CONFIG(APB1RST, 0U)
46 #define GD32_RESET_TIMER5     GD32_RESET_CONFIG(APB1RST, 4U)
47 #define GD32_RESET_TIMER6     GD32_RESET_CONFIG(APB1RST, 5U)
48 #define GD32_RESET_WWDGT      GD32_RESET_CONFIG(APB1RST, 11U)
49 #define GD32_RESET_SPI1       GD32_RESET_CONFIG(APB1RST, 14U)
50 #define GD32_RESET_USART1     GD32_RESET_CONFIG(APB1RST, 17U)
51 #define GD32_RESET_USART2     GD32_RESET_CONFIG(APB1RST, 18U)
52 #define GD32_RESET_I2C0       GD32_RESET_CONFIG(APB1RST, 21U)
53 #define GD32_RESET_I2C1       GD32_RESET_CONFIG(APB1RST, 22U)
54 #define GD32_RESET_BKP        GD32_RESET_CONFIG(APB1RST, 26U)
55 #define GD32_RESET_PMU        GD32_RESET_CONFIG(APB1RST, 28U)
56 #define GD32_RESET_DAC        GD32_RESET_CONFIG(APB1RST, 29U)
57 
58 /* APB2 peripherals */
59 #define GD32_RESET_SYSCFG     GD32_RESET_CONFIG(APB2RST, 0U)
60 #define GD32_RESET_CMP        GD32_RESET_CONFIG(APB2RST, 1U)
61 #define GD32_RESET_ADC0       GD32_RESET_CONFIG(APB2RST, 9U)
62 #define GD32_RESET_ADC1       GD32_RESET_CONFIG(APB2RST, 10U)
63 #define GD32_RESET_TIMER0     GD32_RESET_CONFIG(APB2RST, 11U)
64 #define GD32_RESET_SPI0       GD32_RESET_CONFIG(APB2RST, 12U)
65 #define GD32_RESET_TIMER7     GD32_RESET_CONFIG(APB2RST, 13U)
66 #define GD32_RESET_USART0     GD32_RESET_CONFIG(APB2RST, 14U)
67 #define GD32_RESET_TIMER19    GD32_RESET_CONFIG(APB2RST, 20U)
68 #define GD32_RESET_TIMER20    GD32_RESET_CONFIG(APB2RST, 21U)
69 #define GD32_RESET_TRIGSEL    GD32_RESET_CONFIG(APB2RST, 29U)
70 #define GD32_RESET_CAN0       GD32_RESET_CONFIG(APB2RST, 30U)
71 #define GD32_RESET_CAN1       GD32_RESET_CONFIG(APB2RST, 31U)
72 
73 /** @} */
74 
75 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32A50X_H_ */
76