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Searched refs:GD32_CLOCK_CONFIG (Results 1 – 9 of 9) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dgd32f4xx-clocks.h32 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHB1EN, 0U)
33 #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHB1EN, 1U)
34 #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHB1EN, 2U)
35 #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHB1EN, 3U)
36 #define GD32_CLOCK_GPIOE GD32_CLOCK_CONFIG(AHB1EN, 4U)
37 #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHB1EN, 5U)
38 #define GD32_CLOCK_GPIOG GD32_CLOCK_CONFIG(AHB1EN, 6U)
39 #define GD32_CLOCK_GPIOH GD32_CLOCK_CONFIG(AHB1EN, 7U)
40 #define GD32_CLOCK_GPIOI GD32_CLOCK_CONFIG(AHB1EN, 8U)
41 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHB1EN, 12U)
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Dgd32e50x-clocks.h30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_USBHS GD32_CLOCK_CONFIG(AHBEN, 12U)
37 #define GD32_CLOCK_ULPI GD32_CLOCK_CONFIG(AHBEN, 13U)
38 #define GD32_CLOCK_ENET GD32_CLOCK_CONFIG(AHBEN, 14U)
39 #define GD32_CLOCK_ENETTX GD32_CLOCK_CONFIG(AHBEN, 15U)
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Dgd32f403-clocks.h30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_SDIO GD32_CLOCK_CONFIG(AHBEN, 10U)
37 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
40 #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
41 #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U)
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Dgd32e10x-clocks.h30 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
32 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
36 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
39 #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
40 #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
41 #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U)
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Dgd32l23x-clocks.h29 #define GD32_CLOCK_DMA GD32_CLOCK_CONFIG(AHB1EN, 0U)
30 #define GD32_CLOCK_SRAM0 GD32_CLOCK_CONFIG(AHB1EN, 2U)
31 #define GD32_CLOCK_FMC GD32_CLOCK_CONFIG(AHB1EN, 4U)
32 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHB1EN, 6U)
33 #define GD32_CLOCK_SRAM1 GD32_CLOCK_CONFIG(AHB1EN, 7U)
34 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHB1EN, 17U)
35 #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHB1EN, 18U)
36 #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHB1EN, 19U)
37 #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHB1EN, 20U)
38 #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHB1EN, 22U)
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Dgd32a50x-clocks.h29 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
30 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
31 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
32 #define GD32_CLOCK_DMAMUX GD32_CLOCK_CONFIG(AHBEN, 3U)
33 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
34 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
35 #define GD32_CLOCK_MFCOM GD32_CLOCK_CONFIG(AHBEN, 14U)
36 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHBEN, 17U)
37 #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHBEN, 18U)
38 #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHBEN, 19U)
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Dgd32vf103-clocks.h29 #define GD32_CLOCK_DMA0 GD32_CLOCK_CONFIG(AHBEN, 0U)
30 #define GD32_CLOCK_DMA1 GD32_CLOCK_CONFIG(AHBEN, 1U)
31 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
32 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
33 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
34 #define GD32_CLOCK_EXMC GD32_CLOCK_CONFIG(AHBEN, 8U)
35 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
38 #define GD32_CLOCK_TIMER1 GD32_CLOCK_CONFIG(APB1EN, 0U)
39 #define GD32_CLOCK_TIMER2 GD32_CLOCK_CONFIG(APB1EN, 1U)
40 #define GD32_CLOCK_TIMER3 GD32_CLOCK_CONFIG(APB1EN, 2U)
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Dgd32f3x0-clocks.h30 #define GD32_CLOCK_DMA GD32_CLOCK_CONFIG(AHBEN, 0U)
31 #define GD32_CLOCK_SRAMSP GD32_CLOCK_CONFIG(AHBEN, 2U)
32 #define GD32_CLOCK_FMCSP GD32_CLOCK_CONFIG(AHBEN, 4U)
33 #define GD32_CLOCK_CRC GD32_CLOCK_CONFIG(AHBEN, 6U)
34 #define GD32_CLOCK_USBFS GD32_CLOCK_CONFIG(AHBEN, 12U)
35 #define GD32_CLOCK_GPIOA GD32_CLOCK_CONFIG(AHBEN, 17U)
36 #define GD32_CLOCK_GPIOB GD32_CLOCK_CONFIG(AHBEN, 18U)
37 #define GD32_CLOCK_GPIOC GD32_CLOCK_CONFIG(AHBEN, 19U)
38 #define GD32_CLOCK_GPIOD GD32_CLOCK_CONFIG(AHBEN, 20U)
39 #define GD32_CLOCK_GPIOF GD32_CLOCK_CONFIG(AHBEN, 22U)
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Dgd32-clocks-common.h20 #define GD32_CLOCK_CONFIG(reg, bit) \ macro