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Searched refs:DT_INST_CLOCKS_CELL_BY_NAME (Results 1 – 24 of 24) sorted by relevance

/Zephyr-latest/drivers/ethernet/
Deth_dwmac_stm32h7x.c36 .bus = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bus),
37 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bits),
40 .bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bus),
41 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bits),
44 .bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bus),
45 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bits),
Deth_stm32_hal.c1527 .pclken = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bus),
1528 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bits)},
1529 .pclken_tx = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bus),
1530 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bits)},
1531 .pclken_rx = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bus),
1532 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bits)},
1534 .pclken_ptp = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_ptp, bus),
1535 .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_ptp, bits)},
/Zephyr-latest/drivers/serial/
Duart_realtek_rts5912.c64 .clk_grp = DT_INST_CLOCKS_CELL_BY_NAME(n, uart##n, clk_grp), \
65 .clk_idx = DT_INST_CLOCKS_CELL_BY_NAME(n, uart##n, clk_idx), \
Duart_sam0.c1278 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
/Zephyr-latest/soc/atmel/sam0/common/
Datmel_sam0_dt.h20 DT_INST_CLOCKS_CELL_BY_NAME(n, cell, offset))
23 BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, name, cell))
/Zephyr-latest/drivers/rtc/
Drtc_rts5912.c148 .rtc_clk_grp = DT_INST_CLOCKS_CELL_BY_NAME(inst, rtc, clk_grp), \
149 .rtc_clk_idx = DT_INST_CLOCKS_CELL_BY_NAME(inst, rtc, clk_idx), \
Drtc_sam0.c579 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id) \
/Zephyr-latest/drivers/mipi_dsi/
Ddsi_stm32.c457 .enr = DT_INST_CLOCKS_CELL_BY_NAME(inst, dsiclk, bits), \
458 .bus = DT_INST_CLOCKS_CELL_BY_NAME(inst, dsiclk, bus), \
461 .enr = DT_INST_CLOCKS_CELL_BY_NAME(inst, refclk, bits), \
462 .bus = DT_INST_CLOCKS_CELL_BY_NAME(inst, refclk, bus), \
465 .enr = DT_INST_CLOCKS_CELL_BY_NAME(inst, pixelclk, bits), \
466 .bus = DT_INST_CLOCKS_CELL_BY_NAME(inst, pixelclk, bus), \
Ddsi_mcux_2l.c657 (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_NAME(id, dphy, name), \
660 (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_NAME(id, esc, name), \
663 (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_NAME(id, pixel, name), \
/Zephyr-latest/include/zephyr/devicetree/
Dclocks.h338 #define DT_INST_CLOCKS_CELL_BY_NAME(inst, name, cell) \ macro
/Zephyr-latest/drivers/dac/
Ddac_sam0.c135 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
/Zephyr-latest/drivers/pwm/
Dpwm_sam0_tcc.c156 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, id), \
Dpwm_sam0_tc.c201 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, id), \
/Zephyr-latest/drivers/timer/
Dsam0_rtc_timer.c262 | GCLK_CLKCTRL_ID(DT_INST_CLOCKS_CELL_BY_NAME(0, gclk, id)); in sys_clock_driver_init()
/Zephyr-latest/drivers/can/
Dcan_sam0.c220 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, id), \
Dcan_renesas_ra.c1117 .mstp = DT_INST_CLOCKS_CELL_BY_NAME(index, dllclk, mstp), \
1118 .stop_bit = DT_INST_CLOCKS_CELL_BY_NAME(index, dllclk, stop_bit), \
/Zephyr-latest/drivers/spi/
Dspi_sam0.c724 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
736 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
Dspi_b_renesas_ra8.c728 .mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_NAME(index, spiclk, \
730 .stop_bit = DT_INST_CLOCKS_CELL_BY_NAME(index, spiclk, stop_bit), \
/Zephyr-latest/drivers/i2c/
Di2c_sam0.c825 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
838 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
/Zephyr-latest/drivers/counter/
Dcounter_sam0_tc32.c421 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
/Zephyr-latest/drivers/adc/
Dadc_sam0.c569 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
/Zephyr-latest/drivers/audio/
Dwm8904.c676 .mclk_name = (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, name)}; \
/Zephyr-latest/drivers/usb_c/tcpc/
Ducpd_numaker.c2355 .pcc.clk_modidx = DT_INST_CLOCKS_CELL_BY_NAME(inst, name, clock_module_index), \
2356 .pcc.clk_src = DT_INST_CLOCKS_CELL_BY_NAME(inst, name, clock_source), \
2357 .pcc.clk_div = DT_INST_CLOCKS_CELL_BY_NAME(inst, name, clock_divider), \
/Zephyr-latest/tests/lib/devicetree/api/src/
Dmain.c2302 zassert_equal(DT_INST_CLOCKS_CELL_BY_NAME(0, clk_a, bits), 7, ""); in ZTEST()
2303 zassert_equal(DT_INST_CLOCKS_CELL_BY_NAME(0, clk_b, bus), 8, ""); in ZTEST()