Searched refs:DMM_IS_REG_CACHEABLE (Results 1 – 2 of 2) sorted by relevance
29 #define DMM_IS_REG_CACHEABLE(node_id) \ macro38 (DMM_IS_REG_CACHEABLE(node_id) ? CONFIG_DCACHE_LINE_SIZE : sizeof(uint8_t))42 #define DMM_IS_REG_CACHEABLE(node_id) 0
39 #define UARTE_IS_CACHEABLE(idx) DMM_IS_REG_CACHEABLE(DT_PHANDLE(UARTE(idx), memory_regions))
