Searched refs:DIVN_CLK (Results 1 – 1 of 1) sorted by relevance
28 #define DIVN_CLK 32000000 /* DIVN clock: fixed @32MHz */ macro29 #define SCLK_FREQ_2MHZ (DIVN_CLK / 14) /* 2.285714 MHz*/30 #define SCLK_FREQ_4MHZ (DIVN_CLK / 8) /* 4 MHz */31 #define SCLK_FREQ_8MHZ (DIVN_CLK / 4) /* 8 MHz */32 #define SCLK_FREQ_16MHZ (DIVN_CLK / 2) /* 16 MHz */
