Searched refs:D3CCIPR_REG (Results 1 – 2 of 2) sorted by relevance
| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32h7_clock.h | 93 #define D3CCIPR_REG 0x58 macro
128 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG)
129 #define I2C4_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D3CCIPR_REG)
130 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 10, D3CCIPR_REG)
131 #define LPTIM345_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 13, D3CCIPR_REG)
132 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 16, D3CCIPR_REG)
133 #define SAI4A_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 21, D3CCIPR_REG)
134 #define SAI4B_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 24, D3CCIPR_REG)
135 #define SPI6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 28, D3CCIPR_REG)
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| D | stm32h7rs_clock.h | 88 #define D3CCIPR_REG 0x54 macro
119 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG)
120 #define SPI45_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 4, D3CCIPR_REG)
121 #define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 8, D3CCIPR_REG)
122 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, D3CCIPR_REG)
123 #define SAI2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 20, D3CCIPR_REG)
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