Searched refs:CY_SYSCLK_DIV_8_BIT (Results 1 – 4 of 4) sorted by relevance
10 #define CY_SYSCLK_DIV_8_BIT 0 macro
377 Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0u, 0u); in Cy_SystemInit()378 Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0u); in Cy_SystemInit()
389 CY_SYSCLK_DIV_8_BIT, in spi_psoc6_init()391 Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, in spi_psoc6_init()393 Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, in spi_psoc6_init()
36 #define UART_PSOC6_UART_CLK_DIV_TYPE (CY_SYSCLK_DIV_8_BIT)
