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Searched refs:CYCLES_PER_TICK (Results 1 – 11 of 11) sorted by relevance

/Zephyr-latest/drivers/timer/
Dsam0_rtc_timer.c41 #define CYCLES_PER_TICK (RTC_CLOCK_HW_CYCLES_PER_SEC \ macro
45 #define MAX_TICKS (UINT32_MAX / CYCLES_PER_TICK - 2)
56 BUILD_ASSERT(CYCLES_PER_TICK > TICK_THRESHOLD,
67 BUILD_ASSERT(CYCLES_PER_TICK > 1,
162 uint32_t ticks = (count - rtc_last) / CYCLES_PER_TICK; in rtc_isr()
165 rtc_last += ticks * CYCLES_PER_TICK; in rtc_isr()
195 uint32_t timeout = ticks * CYCLES_PER_TICK + count % CYCLES_PER_TICK; in sys_clock_set_timeout()
198 timeout = DIV_ROUND_UP(timeout, CYCLES_PER_TICK) * CYCLES_PER_TICK; in sys_clock_set_timeout()
201 timeout += CYCLES_PER_TICK; in sys_clock_set_timeout()
235 return (rtc_count() - rtc_last) / CYCLES_PER_TICK; in sys_clock_elapsed()
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Dapic_timer.c43 #define CYCLES_PER_TICK \ macro
46 BUILD_ASSERT(CYCLES_PER_TICK >= 1, "APIC timer: bad CYCLES_PER_TICK");
54 total_cycles += CYCLES_PER_TICK; in isr()
81 return cycles + (CYCLES_PER_TICK - ccr_2nd); in sys_clock_cycle_get_64()
110 x86_write_loapic(LOAPIC_TIMER_ICR, CYCLES_PER_TICK); in sys_clock_driver_init()
Dmchp_mec5_ktimer.c56 #define CYCLES_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) macro
68 #define MAX_TICKS (RTIMER_MAX / CYCLES_PER_TICK)
94 static uint32_t cached_icr = CYCLES_PER_TICK;
162 full_cycles = full_ticks * CYCLES_PER_TICK; in sys_clock_set_timeout()
178 partial_cycles = CYCLES_PER_TICK - (total_cycles % CYCLES_PER_TICK); in sys_clock_set_timeout()
213 ticks /= CYCLES_PER_TICK; in sys_clock_elapsed()
233 mec_hal_rtimer_stop_and_load(rtimer, MAX_TICKS * CYCLES_PER_TICK, RTIMER_START_VAL); in mec5_ktimer_isr()
236 cached_icr = MAX_TICKS * CYCLES_PER_TICK; in mec5_ktimer_isr()
244 ticks /= CYCLES_PER_TICK; in mec5_ktimer_isr()
265 uint32_t temp = total_cycles + CYCLES_PER_TICK; in mec5_ktimer_isr()
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Drealtek_rts5912_rtmr.c24 #define CYCLES_PER_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) macro
40 #define MAX_TICKS ((k_ticks_t)(RTMR_COUNTER_MAX / CYCLES_PER_TICK) - 1)
77 rtmr_restart(RTMR_COUNTER_MAX * CYCLES_PER_TICK); in rtmr_isr()
80 previous_cnt = RTMR_COUNTER_MAX * CYCLES_PER_TICK; in rtmr_isr()
90 ticks /= CYCLES_PER_TICK; in rtmr_isr()
122 full_cycles = full_ticks * CYCLES_PER_TICK; in sys_clock_set_timeout()
135 partial_cycles = CYCLES_PER_TICK - (accumulated_cycles % CYCLES_PER_TICK); in sys_clock_set_timeout()
163 ticks /= CYCLES_PER_TICK; in sys_clock_elapsed()
174 previous_cnt = CYCLES_PER_TICK; in sys_clock_idle_exit()
Dmchp_xec_rtos_timer.c53 #define CYCLES_PER_TICK \ macro
87 #define MAX_TICKS (TIMER_MAX / CYCLES_PER_TICK)
105 static uint32_t cached_icr = CYCLES_PER_TICK;
213 full_cycles = full_ticks * CYCLES_PER_TICK; in sys_clock_set_timeout()
229 partial_cycles = CYCLES_PER_TICK - (total_cycles % CYCLES_PER_TICK); in sys_clock_set_timeout()
264 ticks /= CYCLES_PER_TICK; in sys_clock_elapsed()
284 timer_restart(MAX_TICKS * CYCLES_PER_TICK); in xec_rtos_timer_isr()
287 cached_icr = MAX_TICKS * CYCLES_PER_TICK; in xec_rtos_timer_isr()
295 ticks /= CYCLES_PER_TICK; in xec_rtos_timer_isr()
318 uint32_t temp = total_cycles + CYCLES_PER_TICK; in xec_rtos_timer_isr()
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Dwch_systick_ch32v00x.c26 #define CYCLES_PER_TICK (CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) macro
37 ch32v00x_systick_count += CYCLES_PER_TICK; /* Track cycles. */ in ch32v00x_systick_irq()
56 SYSTICK->CMP = CYCLES_PER_TICK; in ch32v00x_systick_init()
Dxlnx_psttc_timer.c26 #define CYCLES_PER_TICK (CYCLES_PER_SEC / TICKS_PER_SEC) macro
90 ticks = (cycles - last_cycles) / CYCLES_PER_TICK; in ttc_isr()
96 update_match(cycles, cycles + CYCLES_PER_TICK); in ttc_isr()
119 next_cycles = cycles + ((uint32_t)ticks * CYCLES_PER_TICK); in sys_clock_set_timeout()
136 return (cycles - last_cycles) / CYCLES_PER_TICK; in sys_clock_elapsed()
185 CYCLES_NEXT_MAX : CYCLES_PER_TICK; in sys_clock_driver_init()
Drv32m1_lptmr_timer.c27 #define CYCLES_PER_TICK (CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) macro
57 cycle_count += CYCLES_PER_TICK; /* Track cycles. */ in lptmr_irq_handler()
138 SYSTEM_TIMER_INSTANCE->CMR = CYCLES_PER_TICK; in sys_clock_driver_init()
Dmcux_lptmr_timer.c55 #define CYCLES_PER_TICK ((uint32_t)((uint64_t)sys_clock_hw_cycles_per_sec() \ macro
97 cycles += CYCLES_PER_TICK; in mcux_lptmr_timer_isr()
126 LPTMR_SetTimerPeriod(LPTMR_BASE, CYCLES_PER_TICK); in sys_clock_driver_init()
Drcar_cmt_timer.c24 #define CYCLES_PER_TICK (CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC) macro
34 BUILD_ASSERT(CYCLES_PER_TICK > 1,
129 sys_write32(CYCLES_PER_TICK, TIMER_BASE_ADDR + CMCOR0_OFFSET); in sys_clock_driver_init()
Dcc13xx_cc26xx_rtc_timer.c42 #define CYCLES_PER_TICK (sys_clock_hw_cycles_per_sec() / \ macro