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Searched refs:CLKCTRL_PLLCX_DIV_MSK (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_control_agilex5_ll.c84 pllcx_div = (sys_read32(mainpllc_reg) & CLKCTRL_PLLCX_DIV_MSK); in get_clk_freq()
91 pllcx_div = (sys_read32(perpllc_reg) & CLKCTRL_PLLCX_DIV_MSK); in get_clk_freq()
191 clock_val /= 1 + (sys_read32(ctr_reg) & CLKCTRL_PLLCX_DIV_MSK); in get_mpu_clk()
Dclock_control_agilex5_ll.h127 #define CLKCTRL_PLLCX_DIV_MSK GENMASK(10, 0) macro