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Searched refs:CLKCTRL_CTLGRP (Results 1 – 2 of 2) sorted by relevance

/Zephyr-latest/drivers/clock_control/
Dclock_control_agilex5_ll.c163 clock_val = get_clk_freq(CLKCTRL_CTLGRP(CORE23CTR), in get_mpu_clk()
167 clock_val = get_clk_freq(CLKCTRL_CTLGRP(CORE01CTR), in get_mpu_clk()
175 ctr_reg = CLKCTRL_CTLGRP(CORE01CTR); in get_mpu_clk()
179 ctr_reg = CLKCTRL_CTLGRP(CORE2CTR); in get_mpu_clk()
183 ctr_reg = CLKCTRL_CTLGRP(CORE3CTR); in get_mpu_clk()
Dclock_control_agilex5_ll.h106 #define CLKCTRL_CTLGRP(_reg) (CLKCTRL_CTLGRP_BASE_ADDR + CLKCTRL_CTLGRP_##_reg) macro