Searched refs:CCR0 (Results 1 – 3 of 3) sorted by relevance
145 *CCR0(config->base) |= CCR0_MASK_RIE | CCR0_MASK_RE; in uart_rzt2m_irq_rx_enable()151 *CCR0(config->base) &= ~CCR0_MASK_RIE; in uart_rzt2m_irq_rx_disable()158 *CCR0(config->base) |= CCR0_MASK_TE | CCR0_MASK_TIE | CCR0_MASK_TEIE; in uart_rzt2m_irq_tx_enable()164 *CCR0(config->base) &= ~(CCR0_MASK_TIE | CCR0_MASK_TEIE); in uart_rzt2m_irq_tx_disable()172 ((*CCR0(config->base) & CCR0_MASK_TIE) == 0)) { in uart_rzt2m_irq_tx_ready()293 *CCR0(config->base) = CCR0_DEFAULT_VALUE; in rzt2m_uart_init()294 while (*CCR0(config->base) & (CCR0_MASK_RE | CCR0_MASK_TE)) { in rzt2m_uart_init()380 *CCR0(config->base) |= (CCR0_MASK_TE | CCR0_MASK_RE); in rzt2m_uart_init()381 while (!(*CCR0(config->base) & CCR0_MASK_RE)) { in rzt2m_uart_init()383 while (!(*CCR0(config->base) & CCR0_MASK_TE)) { in rzt2m_uart_init()
16 #define CCR0(base) ((volatile uint32_t *)(base + 0x08)) macro
314 cfg->regs->CCR0 |= (BIT(R_SCI_B0_CCR0_TIE_Pos) | BIT(R_SCI_B0_CCR0_TEIE_Pos)); in uart_ra_sci_b_irq_tx_enable()321 cfg->regs->CCR0 &= ~(BIT(R_SCI_B0_CCR0_TIE_Pos) | BIT(R_SCI_B0_CCR0_TEIE_Pos)); in uart_ra_sci_b_irq_tx_disable()383 const uint32_t ccr0 = cfg->regs->CCR0; in uart_ra_sci_b_irq_is_pending()652 cfg->regs->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TIE_Msk | R_SCI_B0_CCR0_TEIE_Msk); in disable_tx()661 cfg->regs->CCR0 &= (uint32_t) ~(R_SCI_B0_CCR0_TE_Msk); in disable_tx()
