Searched refs:CCIPR5_REG (Results 1 – 1 of 1) sorted by relevance
| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32h5_clock.h | 87 #define CCIPR5_REG 0xE8 macro
141 #define ADCDAC_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR5_REG)
142 #define DAC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 3, CCIPR5_REG)
143 #define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR5_REG)
144 #define CEC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR5_REG)
145 #define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR5_REG)
146 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, CCIPR5_REG)
147 #define SAI2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 19, CCIPR5_REG)
148 #define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR5_REG)
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