Searched refs:CCIPR2_REG (Results 1 – 7 of 7) sorted by relevance
| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | stm32u5_clock.h | 57 #define CCIPR2_REG 0xE4 macro
84 #define MDF1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR2_REG)
85 #define SAI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG)
86 #define SAI2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG)
87 #define SAE_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 11, CCIPR2_REG)
88 #define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
89 #define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG)
90 #define DSIHOST_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 15, CCIPR2_REG)
91 #define USART6_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR2_REG)
92 #define LTDC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 18, CCIPR2_REG)
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| D | stm32l4_clock.h | 42 #define CCIPR2_REG 0x9C macro
70 #define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
71 #define DFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 2, CCIPR2_REG)
72 #define ADFSDM_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR2_REG)
75 #define DSI_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 12, CCIPR2_REG)
76 #define SDMMC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG)
77 #define OSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG)
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| D | stm32h5_clock.h | 56 #define CCIPR2_REG 0xDC macro
82 #define USART11_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR2_REG)
83 #define USART12_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR2_REG)
84 #define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG)
85 #define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR2_REG)
86 #define LPTIM3_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR2_REG)
87 #define LPTIM4_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR2_REG)
88 #define LPTIM5_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR2_REG)
89 #define LPTIM6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 28, CCIPR2_REG)
97 #define SPI6_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 15, CCIPR2_REG)
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| D | stm32g0_clock.h | 40 #define CCIPR2_REG 0x58 macro
62 #define I2S1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
63 #define I2S2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR2_REG)
64 #define FDCAN_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR2_REG)
65 #define USB_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
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| D | stm32g4_clock.h | 44 #define CCIPR2_REG 0x9C macro
68 #define I2C4_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
69 #define QSPI_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG)
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| D | stm32n6_clock.h | 70 #define CCIPR2_REG 0x148 macro
88 #define ETH1PTP_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
89 #define ETH1CLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
90 #define ETH1_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR2_REG)
91 #define ETH1REFCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 20, CCIPR2_REG)
92 #define ETH1GTXCLK_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR2_REG)
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| D | stm32wba_clock.h | 50 #define CCIPR2_REG 0xE4 macro
65 #define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
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