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Searched refs:BUILD_ASSERT (Results 1 – 25 of 643) sorted by relevance

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/Zephyr-latest/soc/nordic/
Dvalidate_binding_headers.c24 BUILD_ASSERT(NRF_DOMAIN_ID_APPLICATION == NRF_DOMAIN_APPLICATION);
27 BUILD_ASSERT(NRF_DOMAIN_ID_RADIOCORE == NRF_DOMAIN_RADIOCORE);
30 BUILD_ASSERT(NRF_DOMAIN_ID_GLOBALFAST == NRF_DOMAIN_GLOBALFAST);
33 BUILD_ASSERT(NRF_DOMAIN_ID_GLOBALSLOW == NRF_DOMAIN_GLOBALSLOW);
41 BUILD_ASSERT(NRF_OWNER_ID_NONE == NRF_OWNER_NONE);
44 BUILD_ASSERT(NRF_OWNER_ID_APPLICATION == NRF_OWNER_APPLICATION);
47 BUILD_ASSERT(NRF_OWNER_ID_RADIOCORE == NRF_OWNER_RADIOCORE);
Dvalidate_enabled_instances.c50 BUILD_ASSERT(CHECK(0), MSG(0));
52 BUILD_ASSERT(CHECK(1), MSG(1));
53 BUILD_ASSERT(CHECK(2), MSG(2));
54 BUILD_ASSERT(CHECK(3), MSG(3));
55 BUILD_ASSERT(CHECK(00), MSG(00));
56 BUILD_ASSERT(CHECK(20), MSG(20));
57 BUILD_ASSERT(CHECK(21), MSG(21));
58 BUILD_ASSERT(CHECK(22), MSG(22));
59 BUILD_ASSERT(CHECK(30), MSG(30));
62 BUILD_ASSERT(!(SPI_ENABLED(1) && I2C_ENABLED(0)),
/Zephyr-latest/tests/kernel/common/src/
Dpow2.c38 BUILD_ASSERT(sizeof(static_array1) == 1);
39 BUILD_ASSERT(sizeof(static_array2) == 2);
40 BUILD_ASSERT(sizeof(static_array3) == 4);
41 BUILD_ASSERT(sizeof(static_array4) == 4);
42 BUILD_ASSERT(sizeof(static_array5) == 8);
43 BUILD_ASSERT(sizeof(static_array7) == 8);
44 BUILD_ASSERT(sizeof(static_array8) == 8);
45 BUILD_ASSERT(sizeof(static_array9) == 16);
/Zephyr-latest/subsys/bluetooth/common/
Ddummy.c29 BUILD_ASSERT(sizeof(bt_addr_t) == BT_ADDR_SIZE);
30 BUILD_ASSERT(alignof(bt_addr_t) == 1);
31 BUILD_ASSERT(sizeof(bt_addr_le_t) == BT_ADDR_LE_SIZE);
32 BUILD_ASSERT(alignof(bt_addr_le_t) == 1);
41 BUILD_ASSERT(CONFIG_BT_DRIVER_RX_HIGH_PRIO < CONFIG_BT_HCI_TX_PRIO);
59 BUILD_ASSERT(!IS_ENABLED(CONFIG_LOG_MODE_IMMEDIATE), "Immediate logging "
/Zephyr-latest/include/zephyr/arch/arc/
Darch.h101 BUILD_ASSERT(CONFIG_ISR_STACK_SIZE % ARCH_STACK_PTR_ALIGN == 0,
104 BUILD_ASSERT(CONFIG_ARC_EXCEPTION_STACK_SIZE % ARCH_STACK_PTR_ALIGN == 0,
182 BUILD_ASSERT(CONFIG_PRIVILEGED_STACK_SIZE % Z_ARC_MPU_ALIGN == 0,
225 BUILD_ASSERT(CONFIG_PRIVILEGED_STACK_SIZE % Z_ARC_MPU_ALIGN == 0,
308 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? !((size) & ((size) - 1)) : 1, \
310 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? (size) >= Z_ARC_MPU_ALIGN : 1, \
312 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? IS_BUILTIN_MWDT(start) ? \
317 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? (size) % Z_ARC_MPU_ALIGN == 0 : 1, \
319 BUILD_ASSERT(IS_BUILTIN_MWDT(size) ? (size) >= Z_ARC_MPU_ALIGN : 1, \
321 BUILD_ASSERT(IS_BUILTIN_MWDT(start) ? (uintptr_t)(start) % Z_ARC_MPU_ALIGN == 0 : 1, \
[all …]
/Zephyr-latest/drivers/display/
Ddisplay_ili9341.h85 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), gamset) == ILI9341_GAMSET_LEN, \
87 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), ifmode) == ILI9341_IFMODE_LEN, \
89 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), frmctr1) == ILI9341_FRMCTR1_LEN, \
91 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), disctrl) == ILI9341_DISCTRL_LEN, \
93 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrl1) == ILI9341_PWCTRL1_LEN, \
95 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pwctrl2) == ILI9341_PWCTRL2_LEN, \
97 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), vmctrl1) == ILI9341_VMCTRL1_LEN, \
99 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), vmctrl2) == ILI9341_VMCTRL2_LEN, \
101 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), pgamctrl) == ILI9341_PGAMCTRL_LEN, \
103 BUILD_ASSERT(DT_PROP_LEN(DT_INST(n, ilitek_ili9341), ngamctrl) == ILI9341_NGAMCTRL_LEN, \
[all …]
Duc81xx_regs.h114 BUILD_ASSERT(sizeof(struct uc81xx_tres8) == 2);
124 BUILD_ASSERT(sizeof(struct uc81xx_ptl8) == 5);
131 BUILD_ASSERT(sizeof(struct uc81xx_tres16) == 4);
141 BUILD_ASSERT(sizeof(struct uc81xx_ptl16) == 9);
/Zephyr-latest/drivers/fpga/
Dfpga_ice40_common.h31 BUILD_ASSERT(DT_INST_PROP(inst, spi_max_frequency) >= FPGA_ICE40_SPI_HZ_MIN); \
32 BUILD_ASSERT(DT_INST_PROP(inst, spi_max_frequency) <= FPGA_ICE40_SPI_HZ_MAX); \
33 BUILD_ASSERT(DT_INST_PROP(inst, config_delay_us) >= FPGA_ICE40_CONFIG_DELAY_US_MIN); \
34 BUILD_ASSERT(DT_INST_PROP(inst, config_delay_us) <= UINT16_MAX); \
35 BUILD_ASSERT(DT_INST_PROP(inst, creset_delay_us) >= FPGA_ICE40_CRESET_DELAY_US_MIN); \
36 BUILD_ASSERT(DT_INST_PROP(inst, creset_delay_us) <= UINT16_MAX); \
37 BUILD_ASSERT(DT_INST_PROP(inst, leading_clocks) >= FPGA_ICE40_LEADING_CLOCKS_MIN); \
38 BUILD_ASSERT(DT_INST_PROP(inst, leading_clocks) <= UINT8_MAX); \
39 BUILD_ASSERT(DT_INST_PROP(inst, trailing_clocks) >= FPGA_ICE40_TRAILING_CLOCKS_MIN); \
40 BUILD_ASSERT(DT_INST_PROP(inst, trailing_clocks) <= UINT8_MAX); \
/Zephyr-latest/include/zephyr/drivers/stepper/
Dstepper_trinamic.h85 BUILD_ASSERT(IN_RANGE(DT_PROP(node, vstart), TMC_RAMP_VSTART_MIN, \
88 BUILD_ASSERT(IN_RANGE(DT_PROP(node, v1), TMC_RAMP_V1_MIN, \
91 BUILD_ASSERT(IN_RANGE(DT_PROP(node, vmax), TMC_RAMP_VMAX_MIN, \
94 BUILD_ASSERT(IN_RANGE(DT_PROP(node, a1), TMC_RAMP_A1_MIN, \
97 BUILD_ASSERT(IN_RANGE(DT_PROP(node, amax), TMC_RAMP_AMAX_MIN, \
100 BUILD_ASSERT(IN_RANGE(DT_PROP(node, d1), TMC_RAMP_D1_MIN, \
103 BUILD_ASSERT(IN_RANGE(DT_PROP(node, dmax), TMC_RAMP_DMAX_MIN, \
106 BUILD_ASSERT(IN_RANGE(DT_PROP(node, vstop), TMC_RAMP_VSTOP_MIN, \
109 BUILD_ASSERT(IN_RANGE(DT_PROP(node, tzerowait), TMC_RAMP_TZEROWAIT_MIN, \
112 BUILD_ASSERT(IN_RANGE(DT_PROP(node, vcoolthrs), TMC_RAMP_VCOOLTHRS_MIN, \
[all …]
/Zephyr-latest/samples/bluetooth/encrypted_advertising/peripheral/src/
Ddata.h21 BUILD_ASSERT(sizeof(ad_data_0) == AD_DATA_0_SIZE);
25 BUILD_ASSERT(sizeof(ad_data_1) == AD_DATA_1_SIZE);
29 BUILD_ASSERT(sizeof(ad_data_2) == AD_DATA_2_SIZE);
33 BUILD_ASSERT(sizeof(ad_data_3) == AD_DATA_3_SIZE);
37 BUILD_ASSERT(sizeof(ad_data_4) == AD_DATA_4_SIZE);
/Zephyr-latest/drivers/comparator/
Dcomparator_nrf_comp.c95 BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_TH_DOWN(0) < 64);
96 BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_TH_UP(0) < 64);
100 BUILD_ASSERT((COMP_NRF_COMP_PSEL_AIN0 == 0));
101 BUILD_ASSERT((COMP_NRF_COMP_PSEL_AIN7 == 7));
102 BUILD_ASSERT((COMP_NRF_COMP_EXTREFSEL_AIN0 == 0));
103 BUILD_ASSERT((COMP_NRF_COMP_EXTREFSEL_AIN7 == 7));
106 BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_PSEL(0) != COMP_NRF_COMP_PSEL_AIN4);
110 BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_PSEL(0) != COMP_NRF_COMP_PSEL_AIN5);
114 BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_PSEL(0) != COMP_NRF_COMP_PSEL_AIN6);
118 BUILD_ASSERT(SHIM_NRF_COMP_DT_INST_PSEL(0) != COMP_NRF_COMP_PSEL_AIN7);
[all …]
Dcomparator_mcux_acmp.c226 BUILD_ASSERT((int)kACMP_OffsetLevel0 == (int)COMP_MCUX_ACMP_OFFSET_MODE_LEVEL0);
227 BUILD_ASSERT((int)kACMP_OffsetLevel1 == (int)COMP_MCUX_ACMP_OFFSET_MODE_LEVEL1);
231 BUILD_ASSERT((int)kACMP_HysteresisLevel0 == (int)COMP_MCUX_ACMP_HYSTERESIS_MODE_LEVEL0);
232 BUILD_ASSERT((int)kACMP_HysteresisLevel1 == (int)COMP_MCUX_ACMP_HYSTERESIS_MODE_LEVEL1);
233 BUILD_ASSERT((int)kACMP_HysteresisLevel2 == (int)COMP_MCUX_ACMP_HYSTERESIS_MODE_LEVEL2);
234 BUILD_ASSERT((int)kACMP_HysteresisLevel3 == (int)COMP_MCUX_ACMP_HYSTERESIS_MODE_LEVEL3);
237 BUILD_ASSERT((int)kACMP_VrefSourceVin1 == (int)COMP_MCUX_ACMP_DAC_VREF_SOURCE_VIN1);
238 BUILD_ASSERT((int)kACMP_VrefSourceVin2 == (int)COMP_MCUX_ACMP_DAC_VREF_SOURCE_VIN2);
241 BUILD_ASSERT((int)kACMP_PortInputFromDAC == (int)COMP_MCUX_ACMP_PORT_INPUT_DAC);
242 BUILD_ASSERT((int)kACMP_PortInputFromMux == (int)COMP_MCUX_ACMP_PORT_INPUT_MUX);
[all …]
/Zephyr-latest/boards/nordic/thingy53/
Dboard.c18 BUILD_ASSERT(CONFIG_THINGY53_INIT_PRIORITY > CONFIG_REGULATOR_FIXED_INIT_PRIORITY,
22 BUILD_ASSERT(CONFIG_THINGY53_INIT_PRIORITY < CONFIG_IEEE802154_NRF5_INIT_PRIO,
28 BUILD_ASSERT(CONFIG_THINGY53_INIT_PRIORITY < CONFIG_SENSOR_INIT_PRIORITY,
/Zephyr-latest/drivers/clock_control/
Dclock_control_npcx.c158 BUILD_ASSERT(OFMCLK <= MAX_OFMCLK, "Exceed maximum OFMCLK setting");
159 BUILD_ASSERT(CORE_CLK <= MAX_OFMCLK && CORE_CLK >= MHZ(4) &&
163 BUILD_ASSERT(CORE_CLK / (FIUDIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
167 BUILD_ASSERT(CORE_CLK / (FIU1DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
171 BUILD_ASSERT(CORE_CLK / (AHB6DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
174 BUILD_ASSERT(APBSRC_CLK / (APB1DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
178 BUILD_ASSERT(APBSRC_CLK / (APB2DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
182 BUILD_ASSERT(APBSRC_CLK / (APB3DIV_VAL + 1) <= (MAX_OFMCLK / 2) &&
187 BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) <= MAX_OFMCLK &&
193 BUILD_ASSERT(OFMCLK / (MCLKD_SL + 1) <= MHZ(50) &&
[all …]
Dclock_control_nrf2_global_hsfll.c31 BUILD_ASSERT(GLOBAL_HSFLL_CLOCK_FREQUENCIES_SIZE == 4);
32 BUILD_ASSERT(GLOBAL_HSFLL_CLOCK_FREQUENCIES_IDX(0) == 64000000);
33 BUILD_ASSERT(GLOBAL_HSFLL_CLOCK_FREQUENCIES_IDX(1) == 128000000);
34 BUILD_ASSERT(GLOBAL_HSFLL_CLOCK_FREQUENCIES_IDX(2) == 256000000);
35 BUILD_ASSERT(GLOBAL_HSFLL_CLOCK_FREQUENCIES_IDX(3) == 320000000);
36 BUILD_ASSERT(GDFS_FREQ_COUNT == 4);
37 BUILD_ASSERT(GDFS_FREQ_HIGH == 0);
38 BUILD_ASSERT(GDFS_FREQ_MEDHIGH == 1);
39 BUILD_ASSERT(GDFS_FREQ_MEDLOW == 2);
40 BUILD_ASSERT(GDFS_FREQ_LOW == 3);
/Zephyr-latest/lib/posix/options/
Duname.c40 BUILD_ASSERT(sizeof(z_name.sysname) >= sizeof("Zephyr"));
41 BUILD_ASSERT(sizeof(z_name.release) >= sizeof(KERNEL_VERSION_STRING));
42 BUILD_ASSERT(sizeof(z_name.version) >= sizeof(UTSNAME_VERSION(VERSION_BUILD)));
43 BUILD_ASSERT(sizeof(z_name.machine) >= sizeof(CONFIG_ARCH));
/Zephyr-latest/soc/nordic/common/
Dsoc_nrf_common.h69 BUILD_ASSERT( \
85 BUILD_ASSERT( \
211 (BUILD_ASSERT(DT_NODE_HAS_COMPAT( \
224 (BUILD_ASSERT(1, \
235 BUILD_ASSERT(!IS_ENABLED(CONFIG_PM_DEVICE) || \
/Zephyr-latest/tests/bsim/bluetooth/host/adv/long_ad/src/
Dad.h37 BUILD_ASSERT(sizeof(test_ad1) > CONFIG_BT_CTLR_ADV_DATA_LEN_MAX);
59 BUILD_ASSERT(sizeof(test_ad2) == CONFIG_BT_CTLR_ADV_DATA_LEN_MAX);
/Zephyr-latest/drivers/pwm/
Dpwm_nxp_s32_emios.c592 BUILD_ASSERT(BIT(DT_PROP(node_id, channel)) & \
597 BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, duty_cycle), \
599 BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, polarity), \
601 BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, input_filter), \
606 BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, period), \
608 BUILD_ASSERT(IN_RANGE(DT_PROP(node_id, period), EMIOS_PWM_IP_MIN_CNT_VAL + 1, \
611 BUILD_ASSERT(DT_PROP(node_id, duty_cycle) <= DT_PROP(node_id, period), \
613 BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, master_bus), \
615 BUILD_ASSERT(DT_PROP(node_id, dead_time) == 0, \
617 BUILD_ASSERT(DT_PROP(node_id, phase_shift) == 0, \
[all …]
/Zephyr-latest/include/zephyr/misc/
Dlorem_ipsum.h32 BUILD_ASSERT(sizeof(LOREM_IPSUM_SHORT) == LOREM_IPSUM_SHORT_STRLEN + 1);
55 BUILD_ASSERT(sizeof(LOREM_IPSUM) == LOREM_IPSUM_STRLEN + 1);
/Zephyr-latest/include/zephyr/posix/
Dposix_types.h99 BUILD_ASSERT(sizeof(pthread_attr_t) >= sizeof(struct pthread_attr));
117 BUILD_ASSERT(sizeof(pthread_mutexattr_t) >= sizeof(struct pthread_mutexattr));
129 BUILD_ASSERT(sizeof(pthread_condattr_t) >= sizeof(struct pthread_condattr));
151 BUILD_ASSERT(sizeof(pthread_once_t) >= sizeof(struct pthread_once));
/Zephyr-latest/arch/arm/core/cortex_a_r/
Dsmp.c62 BUILD_ASSERT(offsetof(struct boot_params, mpid) == BOOT_PARAM_MPID_OFFSET);
63 BUILD_ASSERT(offsetof(struct boot_params, irq_sp) == BOOT_PARAM_IRQ_SP_OFFSET);
64 BUILD_ASSERT(offsetof(struct boot_params, fiq_sp) == BOOT_PARAM_FIQ_SP_OFFSET);
65 BUILD_ASSERT(offsetof(struct boot_params, abt_sp) == BOOT_PARAM_ABT_SP_OFFSET);
66 BUILD_ASSERT(offsetof(struct boot_params, udf_sp) == BOOT_PARAM_UDF_SP_OFFSET);
67 BUILD_ASSERT(offsetof(struct boot_params, svc_sp) == BOOT_PARAM_SVC_SP_OFFSET);
68 BUILD_ASSERT(offsetof(struct boot_params, sys_sp) == BOOT_PARAM_SYS_SP_OFFSET);
69 BUILD_ASSERT(offsetof(struct boot_params, voting) == BOOT_PARAM_VOTING_OFFSET);
/Zephyr-latest/tests/bsim/bluetooth/host/adv/encrypted/css_sample_data/src/
Dcommon.h92 BUILD_ASSERT(sizeof(sample_ad_data_1) == SIZE_SAMPLE_AD_DATA_1);
99 BUILD_ASSERT(sizeof(sample_ead_1) == SIZE_SAMPLE_EAD_1);
120 BUILD_ASSERT(sizeof(sample_ad_data_2) == SIZE_SAMPLE_AD_DATA_2);
126 BUILD_ASSERT(sizeof(sample_ead_2) == SIZE_SAMPLE_EAD_2);
/Zephyr-latest/include/zephyr/ipc/
Dpbuf.h146 BUILD_ASSERT(dcache_align >= 0, \
148 BUILD_ASSERT((size) > 0 && IS_PTR_ALIGNED_BYTES(size, _PBUF_IDX_SIZE), \
150 BUILD_ASSERT(IS_PTR_ALIGNED_BYTES(mem_addr, MAX(dcache_align, _PBUF_IDX_SIZE)), \
152 BUILD_ASSERT(size >= (MAX(dcache_align, _PBUF_IDX_SIZE) + _PBUF_IDX_SIZE + \
/Zephyr-latest/drivers/firmware/scmi/
Dmailbox.h73 BUILD_ASSERT(DT_INST_PROP_LEN(inst, mboxes) != 1 || \
78 BUILD_ASSERT(DT_INST_PROP_LEN(inst, mboxes) != 2 || \
83 BUILD_ASSERT(DT_INST_PROP_LEN(inst, shmem) == 1, \
86 BUILD_ASSERT(DT_INST_PROP_LEN(inst, mboxes) <= 2, \

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