1 /* 2 * Copyright (c) 2023 Google LLC 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SENSOR_BMA4XX_BMA4XX_H_ 8 #define ZEPHYR_DRIVERS_SENSOR_BMA4XX_BMA4XX_H_ 9 10 #include <zephyr/kernel.h> 11 #include <zephyr/device.h> 12 #include <zephyr/drivers/sensor.h> 13 14 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 15 #include <zephyr/drivers/spi.h> 16 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ 17 18 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 19 #include <zephyr/drivers/i2c.h> 20 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ 21 22 /* 23 * Register definitions 24 */ 25 26 #define BMA4XX_REG_CHIP_ID (0x00) 27 #define BMA4XX_REG_ERROR (0x02) 28 #define BMA4XX_REG_STATUS (0x03) 29 #define BMA4XX_REG_DATA_0 (0x0A) 30 #define BMA4XX_REG_DATA_1 (0x0B) 31 #define BMA4XX_REG_DATA_2 (0x0C) 32 #define BMA4XX_REG_DATA_3 (0x0D) 33 #define BMA4XX_REG_DATA_4 (0x0E) 34 #define BMA4XX_REG_DATA_5 (0x0F) 35 #define BMA4XX_REG_DATA_6 (0x10) 36 #define BMA4XX_REG_DATA_7 (0x11) 37 #define BMA4XX_REG_DATA_8 (0x12) 38 #define BMA4XX_REG_DATA_9 (0x13) 39 #define BMA4XX_REG_DATA_10 (0x14) 40 #define BMA4XX_REG_DATA_11 (0x15) 41 #define BMA4XX_REG_DATA_12 (0x16) 42 #define BMA4XX_REG_DATA_13 (0x17) 43 #define BMA4XX_REG_SENSORTIME_0 (0x18) 44 #define BMA4XX_REG_INT_STAT_0 (0x1C) 45 #define BMA4XX_REG_INT_STAT_1 (0x1D) 46 #define BMA4XX_REG_STEP_CNT_OUT_0 (0x1E) 47 #define BMA4XX_REG_HIGH_G_OUT (0x1F) 48 #define BMA4XX_REG_TEMPERATURE (0x22) 49 #define BMA4XX_REG_FIFO_LENGTH_0 (0x24) 50 #define BMA4XX_REG_FIFO_LENGTH_1 (0x25) 51 #define BMA4XX_REG_FIFO_DATA (0x26) 52 #define BMA4XX_REG_ACTIVITY_OUT (0x27) 53 #define BMA4XX_REG_ORIENTATION_OUT (0x28) 54 #define BMA4XX_REG_ACCEL_CONFIG (0x40) 55 #define BMA4XX_REG_ACCEL_RANGE (0x41) 56 #define BMA4XX_REG_AUX_CONFIG (0x44) 57 #define BMA4XX_REG_FIFO_DOWN (0x45) 58 #define BMA4XX_REG_FIFO_WTM_0 (0x46) 59 #define BMA4XX_REG_FIFO_CONFIG_0 (0x48) 60 #define BMA4XX_REG_FIFO_CONFIG_1 (0x49) 61 #define BMA4XX_REG_AUX_DEV_ID (0x4B) 62 #define BMA4XX_REG_AUX_IF_CONF (0x4C) 63 #define BMA4XX_REG_AUX_RD (0x4D) 64 #define BMA4XX_REG_AUX_WR (0x4E) 65 #define BMA4XX_REG_AUX_WR_DATA (0x4F) 66 #define BMA4XX_REG_INT1_IO_CTRL (0x53) 67 #define BMA4XX_REG_INT2_IO_CTRL (0x54) 68 #define BMA4XX_REG_INT_LATCH (0x55) 69 #define BMA4XX_REG_INT_MAP_1 (0x56) 70 #define BMA4XX_REG_INT_MAP_2 (0x57) 71 #define BMA4XX_REG_INT_MAP_DATA (0x58) 72 #define BMA4XX_REG_INIT_CTRL (0x59) 73 #define BMA4XX_REG_RESERVED_REG_5B (0x5B) 74 #define BMA4XX_REG_RESERVED_REG_5C (0x5C) 75 #define BMA4XX_REG_FEATURE_CONFIG (0x5E) 76 #define BMA4XX_REG_IF_CONFIG (0x6B) 77 #define BMA4XX_REG_ACC_SELF_TEST (0x6D) 78 #define BMA4XX_REG_NV_CONFIG (0x70) 79 #define BMA4XX_REG_OFFSET_0 (0x71) 80 #define BMA4XX_REG_OFFSET_1 (0x72) 81 #define BMA4XX_REG_OFFSET_2 (0x73) 82 #define BMA4XX_REG_POWER_CONF (0x7C) 83 #define BMA4XX_REG_POWER_CTRL (0x7D) 84 #define BMA4XX_REG_CMD (0x7E) 85 86 /* 87 * Bit positions and masks 88 */ 89 90 #define BMA4XX_BIT_ADV_PWR_SAVE BIT(0) 91 92 #define BMA4XX_MASK_ACC_CONF_ODR GENMASK(3, 0) 93 #define BMA4XX_MASK_ACC_CONF_BWP GENMASK(6, 4) 94 #define BMA4XX_SHIFT_ACC_CONF_BWP (4) 95 96 #define BMA4XX_MASK_ACC_RANGE GENMASK(1, 0) 97 98 #define BMA4XX_BIT_ACC_PERF_MODE BIT(7) 99 100 #define BMA4XX_BIT_ACC_EN BIT(2) 101 102 /* INT_STATUS_1 accelerometer data ready to interrupt */ 103 #define BMA4XX_ACC_DRDY_INT BIT(7) 104 105 /* CMD: Clears all data in FIFO, does not change FIFO_CONFIG and FIFO_DOWNS register */ 106 #define BMA4XX_CMD_FIFO_FLUSH (0xB0) 107 108 /* FIFO_CONFIG_1 enable: Store Accelerometer data in FIFO (all 3 axes) */ 109 #define BMA4XX_FIFO_ACC_EN BIT(6) 110 111 /* Bandwidth parameters */ 112 #define BMA4XX_BWP_OSR4_AVG1 (0x0) 113 #define BMA4XX_BWP_OSR2_AVG2 (0x1) 114 #define BMA4XX_BWP_NORM_AVG4 (0x2) 115 #define BMA4XX_BWP_CIC_AVG8 (0x3) 116 #define BMA4XX_BWP_RES_AVG16 (0x4) 117 #define BMA4XX_BWP_RES_AVG32 (0x5) 118 #define BMA4XX_BWP_RES_AVG64 (0x6) 119 #define BMA4XX_BWP_RES_AVG128 (0x7) 120 121 /* Full-scale ranges */ 122 #define BMA4XX_RANGE_2G (0x0) 123 #define BMA4XX_RANGE_4G (0x1) 124 #define BMA4XX_RANGE_8G (0x2) 125 #define BMA4XX_RANGE_16G (0x3) 126 127 /* Output data rates (ODR) */ 128 #define BMA4XX_ODR_RESERVED (0x00) 129 #define BMA4XX_ODR_0_78125 (0x01) 130 #define BMA4XX_ODR_1_5625 (0x02) 131 #define BMA4XX_ODR_3_125 (0x03) 132 #define BMA4XX_ODR_6_25 (0x04) 133 #define BMA4XX_ODR_12_5 (0x05) 134 #define BMA4XX_ODR_25 (0x06) 135 #define BMA4XX_ODR_50 (0x07) 136 #define BMA4XX_ODR_100 (0x08) 137 #define BMA4XX_ODR_200 (0x09) 138 #define BMA4XX_ODR_400 (0x0a) 139 #define BMA4XX_ODR_800 (0x0b) 140 #define BMA4XX_ODR_1600 (0x0c) 141 #define BMA4XX_ODR_3200 (0x0d) 142 #define BMA4XX_ODR_6400 (0x0e) 143 #define BMA4XX_ODR_12800 (0x0f) 144 145 /* 146 * BMA4xx commands 147 */ 148 149 #define BMA4XX_CMD_SOFT_RESET (0xB6) 150 151 #define BMA4XX_CHIP_ID_BMA422 (0x12) 152 #define BMA4XX_CHIP_ID_BMA423 (0x13) 153 154 /* 155 * Other constants 156 */ 157 158 /* Each bit count is 3.9mG or 3900uG */ 159 #define BMA4XX_OFFSET_MICROG_PER_BIT (3900) 160 #define BMA4XX_OFFSET_MICROG_MIN (INT8_MIN * BMA4XX_OFFSET_MICROG_PER_BIT) 161 #define BMA4XX_OFFSET_MICROG_MAX (INT8_MAX * BMA4XX_OFFSET_MICROG_PER_BIT) 162 163 /* Range is -104C to 150C. Use shift of 8 (+/-256) */ 164 #define BMA4XX_TEMP_SHIFT (8) 165 166 /* The total number of used registers specified in bma422 datasheet is 7E */ 167 #define BMA4XX_NUM_REGS 0x7E 168 169 /* 170 * Types 171 */ 172 173 union bma4xx_bus_cfg { 174 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) 175 struct i2c_dt_spec i2c; 176 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */ 177 178 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) 179 struct spi_dt_spec spi; 180 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */ 181 }; 182 183 struct bma4xx_config { 184 int (*bus_init)(const struct device *dev); 185 const union bma4xx_bus_cfg bus_cfg; 186 }; 187 188 /** Used to implement bus-specific R/W operations. See bma4xx_i2c.c and 189 * bma4xx_spi.c. 190 */ 191 struct bma4xx_hw_operations { 192 int (*read_data)(const struct device *dev, uint8_t reg_addr, uint8_t *value, uint8_t len); 193 int (*write_data)(const struct device *dev, uint8_t reg_addr, uint8_t *value, uint8_t len); 194 int (*read_reg)(const struct device *dev, uint8_t reg_addr, uint8_t *value); 195 int (*write_reg)(const struct device *dev, uint8_t reg_addr, uint8_t value); 196 int (*update_reg)(const struct device *dev, uint8_t reg_addr, uint8_t mask, uint8_t value); 197 }; 198 199 struct bma4xx_data { 200 /** Current full-scale range setting as a register value */ 201 uint8_t accel_fs_range; 202 /** Current bandwidth parameter (BWP) as a register value */ 203 uint8_t accel_bwp; 204 /** Current output data rate as a register value */ 205 uint8_t accel_odr; 206 /** Pointer to bus-specific I/O API */ 207 const struct bma4xx_hw_operations *hw_ops; 208 /** Chip ID value stored in BMA4XX_REG_CHIP_ID */ 209 uint8_t chip_id; 210 }; 211 212 /* 213 * RTIO types 214 */ 215 216 struct bma4xx_decoder_header { 217 uint64_t timestamp; 218 uint8_t is_fifo: 1; 219 uint8_t accel_fs: 2; 220 uint8_t reserved: 5; 221 } __attribute__((__packed__)); 222 223 struct bma4xx_encoded_data { 224 struct bma4xx_decoder_header header; 225 struct { 226 /** Set if `accel_xyz` has data */ 227 uint8_t has_accel: 1; 228 /** Set if `temp` has data */ 229 uint8_t has_temp: 1; 230 uint8_t reserved: 6; 231 } __attribute__((__packed__)); 232 int16_t accel_xyz[3]; 233 #ifdef CONFIG_BMA4XX_TEMPERATURE 234 int8_t temp; 235 #endif /* CONFIG_BMA4XX_TEMPERATURE */ 236 }; 237 238 int bma4xx_spi_init(const struct device *dev); 239 int bma4xx_i2c_init(const struct device *dev); 240 241 #endif /* ZEPHYR_DRIVERS_SENSOR_BMA4XX_BMA4XX_H_ */ 242
