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Searched refs:BIT_MASK (Results 1 – 25 of 223) sorted by relevance

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/Zephyr-latest/include/zephyr/drivers/interrupt_controller/
Dintc_vim.h51 #define VIM_GRP_RAW_STS_MASK (BIT_MASK(32))
54 #define VIM_GRP_RAW_STS_MAX (BIT_MASK(32))
60 #define VIM_GRP_STS_MSK_MASK (BIT_MASK(32))
63 #define VIM_GRP_STS_MSK_MAX (BIT_MASK(32))
69 #define VIM_GRP_INTR_EN_SET_MSK_MASK (BIT_MASK(32))
72 #define VIM_GRP_INTR_EN_SET_MSK_MAX (BIT_MASK(32))
78 #define VIM_GRP_INTR_EN_CLR_MSK_MASK (BIT_MASK(32))
81 #define VIM_GRP_INTR_EN_CLR_MSK_MAX (BIT_MASK(32))
87 #define VIM_GRP_IRQSTS_MSK_MASK (BIT_MASK(32))
90 #define VIM_GRP_IRQSTS_MSK_MAX (BIT_MASK(32))
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/Zephyr-latest/tests/kernel/gen_isr_table/src/
Dmultilevel_irq.c66 irq1 = BIT_MASK(CONFIG_1ST_LEVEL_INTERRUPT_BITS) >> 1; in ZTEST()
70 irq1 = BIT_MASK(CONFIG_1ST_LEVEL_INTERRUPT_BITS); in ZTEST()
89 irq1 = BIT_MASK(CONFIG_1ST_LEVEL_INTERRUPT_BITS) >> 1; in ZTEST()
90 irq2 = BIT_MASK(CONFIG_2ND_LEVEL_INTERRUPT_BITS) >> 1; in ZTEST()
94 irq1 = BIT_MASK(CONFIG_1ST_LEVEL_INTERRUPT_BITS); in ZTEST()
95 irq2 = BIT_MASK(CONFIG_2ND_LEVEL_INTERRUPT_BITS); in ZTEST()
115 irq1 = BIT_MASK(CONFIG_1ST_LEVEL_INTERRUPT_BITS) >> 1; in ZTEST()
116 irq2 = BIT_MASK(CONFIG_2ND_LEVEL_INTERRUPT_BITS) >> 1; in ZTEST()
117 irq3 = BIT_MASK(CONFIG_3RD_LEVEL_INTERRUPT_BITS) >> 1; in ZTEST()
121 irq1 = BIT_MASK(CONFIG_1ST_LEVEL_INTERRUPT_BITS); in ZTEST()
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/Zephyr-latest/drivers/audio/
Dtlv320dac310x.h24 #define NDAC_DIV_MASK BIT_MASK(7)
30 #define MDAC_DIV_MASK BIT_MASK(7)
36 #define OSR_MSB_MASK BIT_MASK(2)
39 #define OSR_LSB_MASK BIT_MASK(8)
45 #define IF_CTRL_IFTYPE_MASK BIT_MASK(2)
51 #define IF_CTRL_WLEN_MASK BIT_MASK(2)
63 #define BCLK_DIV_MASK BIT_MASK(7)
69 #define PROC_BLK_SEL_MASK BIT_MASK(5)
92 #define HEADPHONE_DRV_CM_MASK (BIT_MASK(2) << 3)
106 #define HPX_ANA_VOL_MASK (BIT_MASK(7))
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Dtas6422dac.h31 #define MISC_CTRL_1_OTW_CONTROL_MASK (BIT_MASK(2) << 5)
39 #define MISC_CTRL_1_VOLUME_RATE_MASK (BIT_MASK(2) << 2)
45 #define MISC_CTRL_1_GAIN_MASK BIT_MASK(2)
54 #define MISC_CTRL_2_PWM_FREQUENCY_MASK (BIT_MASK(3) << 4)
63 #define MISC_CTRL_2_OUTPUT_PHASE_MASK BIT_MASK(2)
71 #define SAP_CTRL_INPUT_SAMPLING_RATE_MASK (BIT_MASK(2) << 6)
82 #define SAP_CTRL_INPUT_FORMAT_MASK BIT_MASK(3)
94 #define CH_STATE_CTRL_CH1_STATE_CTRL_MASK (BIT_MASK(2) << 6)
96 #define CH_STATE_CTRL_CH2_STATE_CTRL_MASK (BIT_MASK(2) << 4)
106 #define CH_VOLUME_CTRL_VOLUME_MASK BIT_MASK(8)
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/Zephyr-latest/include/zephyr/dt-bindings/adc/
Dadc.h18 #define ADC_ACQ_TIME(unit, value) (((unit) << 14) | ((value) & BIT_MASK(14)))
21 #define ADC_ACQ_TIME_MAX BIT_MASK(14)
23 #define ADC_ACQ_TIME_UNIT(time) (((time) >> 14) & BIT_MASK(2))
24 #define ADC_ACQ_TIME_VALUE(time) ((time) & BIT_MASK(14))
Dstm32_adc.h11 #define STM32_ADC_REG_MASK BIT_MASK(8)
13 #define STM32_ADC_SHIFT_MASK BIT_MASK(5)
15 #define STM32_ADC_MASK_MASK BIT_MASK(3)
17 #define STM32_ADC_REG_VAL_MASK BIT_MASK(3)
19 #define STM32_ADC_REAL_VAL_MASK BIT_MASK(13)
/Zephyr-latest/soc/gd/gd32/gd32f4xx/
Dgd32_regs.h22 #define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
24 #define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
26 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
29 #define RCU_CFG1_TIMERSEL_MSK (BIT_MASK(1) << RCU_CFG1_TIMERSEL_POS)
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dnxp-s32-pinctrl.h24 #define NXP_S32_MSCR_SSS_MASK BIT_MASK(3)
26 #define NXP_S32_IMCR_SSS_MASK BIT_MASK(4)
28 #define NXP_S32_IMCR_IDX_MASK BIT_MASK(9)
30 #define NXP_S32_MSCR_IDX_MASK BIT_MASK(9)
32 #define NXP_S32_MSCR_SIUL2_IDX_MASK BIT_MASK(3)
34 #define NXP_S32_IMCR_SIUL2_IDX_MASK BIT_MASK(3)
/Zephyr-latest/arch/arc/core/mpu/
Darc_mpu_v2_internal.h31 #define AUX_MPU_RDP_REGION_SIZE(size) (((size - 1) & BIT_MASK(2)) | \
32 (((size - 1) & (BIT_MASK(3) << 2)) << 7))
34 #define AUX_MPU_RDP_SIZE_SHIFT(rdp) ((rdp & BIT_MASK(2)) | (((rdp >> 9) & BIT_MASK(3)) << 2))
37 #define AUX_MPU_RDP_ATTR_MASK (BIT_MASK(6) << 3)
38 #define AUX_MPU_RDP_SIZE_MASK ((BIT_MASK(3) << 9) | BIT_MASK(2))
Darc_mpu_v6_internal.h34 #define AUX_MPU_RDP_REGION_SIZE(size) (((size - 1) & BIT_MASK(2)) | \
35 (((size - 1) & (BIT_MASK(3) << 2)) << 7))
37 #define AUX_MPU_RDP_SIZE_SHIFT(rdp) ((rdp & BIT_MASK(2)) | (((rdp >> 9) & BIT_MASK(3)) << 2))
40 #define AUX_MPU_RDP_ATTR_MASK (BIT_MASK(6) << 3)
41 #define AUX_MPU_RDP_SIZE_MASK ((BIT_MASK(3) << 9) | BIT_MASK(2))
/Zephyr-latest/soc/gd/gd32/gd32l23x/
Dgd32_regs.h18 #define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
20 #define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
22 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/soc/gd/gd32/gd32vf103/
Dgd32_regs.h19 #define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
21 #define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/soc/gd/gd32/gd32e10x/
Dgd32_regs.h19 #define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
21 #define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/soc/gd/gd32/gd32e50x/
Dgd32_regs.h19 #define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
21 #define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/soc/gd/gd32/gd32f3x0/
Dgd32_regs.h19 #define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
21 #define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/soc/gd/gd32/gd32f403/
Dgd32_regs.h19 #define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
21 #define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
23 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/soc/gd/gd32/gd32a50x/
Dgd32_regs.h20 #define RCU_CFG0_AHBPSC_MSK (BIT_MASK(4) << RCU_CFG0_AHBPSC_POS)
22 #define RCU_CFG0_APB1PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB1PSC_POS)
24 #define RCU_CFG0_APB2PSC_MSK (BIT_MASK(3) << RCU_CFG0_APB2PSC_POS)
/Zephyr-latest/drivers/i2c/
Di2c_andes_atciic100.h42 #define TARGET_ADDR_MSK BIT_MASK(10)
43 #define DATA_MSK BIT_MASK(8)
46 #define IEN_ALL BIT_MASK(10)
59 #define STATUS_W1C_ALL (BIT_MASK(7) << 3)
82 #define CTRL_DATA_COUNT BIT_MASK(8)
85 #define CMD_MSK BIT_MASK(3)
94 #define SETUP_T_SUDAT (BIT_MASK(5) << 24)
95 #define SETUP_T_SP (BIT_MASK(3) << 21)
96 #define SETUP_T_HDDAT (BIT_MASK(5) << 16)
98 #define SETUP_T_SCLHI (BIT_MASK(9) << 4)
/Zephyr-latest/tests/lib/smf/src/
Dtest_lib_self_transition_smf.c83 BIT_MASK(ROOT_ENTRY),
84 BIT_MASK(PARENT_AB_ENTRY),
85 BIT_MASK(STATE_A_ENTRY),
87 BIT_MASK(STATE_A_RUN),
88 BIT_MASK(STATE_A_EXIT),
89 BIT_MASK(STATE_B_ENTRY),
91 BIT_MASK(STATE_B_1ST_RUN),
93 BIT_MASK(STATE_B_2ND_RUN),
94 BIT_MASK(PARENT_AB_RUN),
95 BIT_MASK(STATE_B_EXIT),
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/Zephyr-latest/drivers/spi/
Dspi_pw.h67 #define PW_SPI_SCR_MASK (BIT_MASK(12) << 8)
84 #define PW_SPI_CTRL1_SPO_SPH_MASK (BIT_MASK(2) << 3)
111 #define PW_SPI_SITF_SITFL_MASK (BIT_MASK(6) << 16)
125 #define PW_SPI_SIRF_SIRFL_MASK (BIT_MASK(6) << 8)
129 #define PW_SPI_WM_MASK BIT_MASK(6)
142 #define PW_SPI_CLKS_MVAL_MASK (BIT_MASK(15) << 1)
145 #define PW_SPI_CLKS_NVAL_MASK (BIT_MASK(15) << 16)
/Zephyr-latest/include/zephyr/arch/arm64/
Dcache.h28 #define CTR_EL0_DMINLINE_MASK BIT_MASK(4)
30 #define CTR_EL0_CWG_MASK BIT_MASK(4)
34 #define CLIDR_EL1_LOC_MASK BIT_MASK(3)
36 #define CLIDR_EL1_CTYPE_MASK BIT_MASK(3)
40 #define CCSIDR_EL1_LN_SZ_MASK BIT_MASK(3)
42 #define CCSIDR_EL1_WAYS_MASK BIT_MASK(10)
44 #define CCSIDR_EL1_SETS_MASK BIT_MASK(15)
/Zephyr-latest/subsys/bluetooth/services/bas/
Dbas_bls.c48 #define BATTERY_MASK (BIT_MASK(1) << BATTERY_SHIFT)
49 #define WIRED_POWER_MASK (BIT_MASK(2) << WIRED_POWER_SHIFT)
50 #define WIRELESS_POWER_MASK (BIT_MASK(2) << WIRELESS_POWER_SHIFT)
51 #define BATTERY_CHARGE_STATE_MASK (BIT_MASK(2) << BATTERY_CHARGE_STATE_SHIFT)
52 #define BATTERY_CHARGE_LEVEL_MASK (BIT_MASK(2) << BATTERY_CHARGE_LEVEL_SHIFT)
53 #define BATTERY_CHARGE_TYPE_MASK (BIT_MASK(3) << BATTERY_CHARGE_TYPE_SHIFT)
54 #define CHARGING_FAULT_MASK (BIT_MASK(3) << CHARGING_FAULT_SHIFT)
66 #define SERVICE_REQUIRED_MASK (BIT_MASK(2) << SERVICE_REQUIRED_SHIFT)
67 #define BATTERY_FAULT_MASK (BIT_MASK(1) << BATTERY_FAULT_SHIFT)
/Zephyr-latest/include/zephyr/audio/
Ddmic.h213 return ((((pdm & BIT_MASK(3)) << 1) | lr) << in dmic_build_channel_map()
214 ((channel & BIT_MASK(3)) * 4U)); in dmic_build_channel_map()
235 channel_map >>= ((channel & BIT_MASK(3)) * 4U); in dmic_parse_channel_map()
237 *pdm = (channel_map >> 1) & BIT_MASK(3); in dmic_parse_channel_map()
254 return ((skew & BIT_MASK(4)) << ((pdm & BIT_MASK(3)) * 4U)); in dmic_build_clk_skew_map()
/Zephyr-latest/arch/arm64/core/
Delf.c61 #define AARCH64_MASK_IMM12 BIT_MASK(12)
62 #define AARCH64_MASK_IMM14 BIT_MASK(14)
63 #define AARCH64_MASK_IMM16 BIT_MASK(16)
64 #define AARCH64_MASK_IMM19 BIT_MASK(19)
65 #define AARCH64_MASK_IMM26 BIT_MASK(26)
68 #define AARCH64_MASK_MOV_OPCODE BIT_MASK(8)
75 #define AARCH64_MASK_ADR_IMMLO BIT_MASK(2)
76 #define AARCH64_MASK_ADR_IMMHI BIT_MASK(19)
380 imm = x & BIT_MASK(len); in imm_reloc_handler()
402 x = (int64_t)(x & ~BIT_MASK(len - 1)) >> (len - 1); in imm_reloc_handler()
/Zephyr-latest/drivers/sensor/ti/tmag5170/
Dtmag5170.c46 #define TMAG5170_CONV_AVG_MASK (BIT_MASK(3U) << TMAG5170_CONV_AVG_POS)
51 #define TMAG5170_MAG_TEMPCO_MASK (BIT_MASK(2U) << TMAG5170_MAG_TEMPCO_POS)
56 #define TMAG5170_OPERATING_MODE_MASK (BIT_MASK(3U) << TMAG5170_OPERATING_MODE_POS)
61 #define TMAG5170_T_CH_EN_MASK (BIT_MASK(1U) << TMAG5170_T_CH_EN_POS)
66 #define TMAG5170_T_RATE_MASK (BIT_MASK(1U) << TMAG5170_T_RATE_POS)
71 #define TMAG5170_ANGLE_EN_MASK (BIT_MASK(2U) << TMAG5170_ANGLE_EN_POS)
76 #define TMAG5170_SLEEPTIME_MASK (BIT_MASK(4U) << TMAG5170_SLEEPTIME_POS)
81 #define TMAG5170_MAG_CH_EN_MASK (BIT_MASK(4U) << TMAG5170_MAG_CH_EN_POS)
86 #define TMAG5170_Z_RANGE_MASK (BIT_MASK(2U) << TMAG5170_Z_RANGE_POS)
91 #define TMAG5170_Y_RANGE_MASK (BIT_MASK(2U) << TMAG5170_Y_RANGE_POS)
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