1 /*
2 * Copyright (c) 2023 honglin leng <a909204013@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT brcm_bcm2711_aux_uart
8
9 /**
10 * @brief BCM2711 Miniuart Serial Driver
11 *
12 */
13
14 #include <zephyr/kernel.h>
15 #include <zephyr/arch/cpu.h>
16 #include <stdbool.h>
17 #include <zephyr/sys/__assert.h>
18 #include <zephyr/init.h>
19 #include <zephyr/drivers/uart.h>
20 #include <zephyr/irq.h>
21
22 #define BCM2711_MU_IO 0x00
23 #define BCM2711_MU_IER 0x04
24 #define BCM2711_MU_IIR 0x08
25 #define BCM2711_MU_LCR 0x0c
26 #define BCM2711_MU_MCR 0x10
27 #define BCM2711_MU_LSR 0x14
28 #define BCM2711_MU_MSR 0x18
29 #define BCM2711_MU_SCRATCH 0x1c
30 #define BCM2711_MU_CNTL 0x20
31 #define BCM2711_MU_STAT 0x24
32 #define BCM2711_MU_BAUD 0x28
33
34 #define BCM2711_MU_IER_TX_INTERRUPT BIT(1)
35 #define BCM2711_MU_IER_RX_INTERRUPT BIT(0)
36
37 #define BCM2711_MU_IIR_RX_INTERRUPT BIT(2)
38 #define BCM2711_MU_IIR_TX_INTERRUPT BIT(1)
39 #define BCM2711_MU_IIR_FLUSH 0xc6
40
41 #define BCM2711_MU_LCR_7BIT 0x02
42 #define BCM2711_MU_LCR_8BIT 0x03
43
44 #define BCM2711_MU_LSR_TX_IDLE BIT(6)
45 #define BCM2711_MU_LSR_TX_EMPTY BIT(5)
46 #define BCM2711_MU_LSR_RX_OVERRUN BIT(1)
47 #define BCM2711_MU_LSR_RX_READY BIT(0)
48
49 #define BCM2711_MU_CNTL_RX_ENABLE BIT(0)
50 #define BCM2711_MU_CNTL_TX_ENABLE BIT(1)
51
52 struct bcm2711_uart_config {
53 DEVICE_MMIO_ROM; /* Must be first */
54 uint32_t baud_rate;
55 uint32_t clocks;
56 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
57 void (*irq_config_func)(const struct device *dev);
58 #endif
59 };
60
61 struct bcm2711_uart_data {
62 DEVICE_MMIO_RAM; /* Must be first */
63 mem_addr_t uart_addr;
64 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
65 uart_irq_callback_user_data_t callback;
66 void *cb_data;
67 #endif
68 };
69
bcm2711_mu_lowlevel_can_getc(mem_addr_t base)70 static bool bcm2711_mu_lowlevel_can_getc(mem_addr_t base)
71 {
72 return sys_read32(base + BCM2711_MU_LSR) & BCM2711_MU_LSR_RX_READY;
73 }
74
bcm2711_mu_lowlevel_can_putc(mem_addr_t base)75 static bool bcm2711_mu_lowlevel_can_putc(mem_addr_t base)
76 {
77 return sys_read32(base + BCM2711_MU_LSR) & BCM2711_MU_LSR_TX_EMPTY;
78 }
79
bcm2711_mu_lowlevel_putc(mem_addr_t base,uint8_t ch)80 static void bcm2711_mu_lowlevel_putc(mem_addr_t base, uint8_t ch)
81 {
82 /* Wait until there is data in the FIFO */
83 while (!bcm2711_mu_lowlevel_can_putc(base)) {
84 ;
85 }
86
87 /* Send the character */
88 sys_write32(ch, base + BCM2711_MU_IO);
89 }
90
bcm2711_mu_lowlevel_init(mem_addr_t base,bool skip_baudrate_config,uint32_t baudrate,uint32_t input_clock)91 static void bcm2711_mu_lowlevel_init(mem_addr_t base, bool skip_baudrate_config,
92 uint32_t baudrate, uint32_t input_clock)
93 {
94 uint32_t divider;
95
96 /* Wait until there is data in the FIFO */
97 while (!bcm2711_mu_lowlevel_can_putc(base)) {
98 ;
99 }
100
101 /* Disable port */
102 sys_write32(0x0, base + BCM2711_MU_CNTL);
103
104 /* Disable interrupts */
105 sys_write32(0x0, base + BCM2711_MU_IER);
106
107 /* Setup 8bit data width and baudrate */
108 sys_write32(BCM2711_MU_LCR_8BIT, base + BCM2711_MU_LCR);
109 if (!skip_baudrate_config) {
110 divider = (input_clock / (baudrate * 8));
111 sys_write32(divider - 1, base + BCM2711_MU_BAUD);
112 }
113
114 /* Enable RX & TX port */
115 sys_write32(BCM2711_MU_CNTL_RX_ENABLE | BCM2711_MU_CNTL_TX_ENABLE, base + BCM2711_MU_CNTL);
116 }
117
118 /**
119 * @brief Initialize UART channel
120 *
121 * This routine is called to reset the chip in a quiescent state.
122 * It is assumed that this function is called only once per UART.
123 *
124 * @param dev UART device struct
125 *
126 * @return 0
127 */
uart_bcm2711_init(const struct device * dev)128 static int uart_bcm2711_init(const struct device *dev)
129 {
130 const struct bcm2711_uart_config *uart_cfg = dev->config;
131 struct bcm2711_uart_data *uart_data = dev->data;
132
133 DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
134 uart_data->uart_addr = DEVICE_MMIO_GET(dev);
135 bcm2711_mu_lowlevel_init(uart_data->uart_addr, 1, uart_cfg->baud_rate, uart_cfg->clocks);
136 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
137 uart_cfg->irq_config_func(dev);
138 #endif
139 return 0;
140 }
141
uart_bcm2711_poll_out(const struct device * dev,unsigned char c)142 static void uart_bcm2711_poll_out(const struct device *dev, unsigned char c)
143 {
144 struct bcm2711_uart_data *uart_data = dev->data;
145
146 bcm2711_mu_lowlevel_putc(uart_data->uart_addr, c);
147 }
148
uart_bcm2711_poll_in(const struct device * dev,unsigned char * c)149 static int uart_bcm2711_poll_in(const struct device *dev, unsigned char *c)
150 {
151 struct bcm2711_uart_data *uart_data = dev->data;
152
153 while (!bcm2711_mu_lowlevel_can_getc(uart_data->uart_addr)) {
154 ;
155 }
156
157 return sys_read32(uart_data->uart_addr + BCM2711_MU_IO) & 0xFF;
158 }
159
160 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
161
uart_bcm2711_fifo_fill(const struct device * dev,const uint8_t * tx_data,int size)162 static int uart_bcm2711_fifo_fill(const struct device *dev,
163 const uint8_t *tx_data,
164 int size)
165 {
166 int num_tx = 0U;
167 struct bcm2711_uart_data *uart_data = dev->data;
168
169 while ((size - num_tx) > 0) {
170 /* Send a character */
171 bcm2711_mu_lowlevel_putc(uart_data->uart_addr, tx_data[num_tx]);
172 num_tx++;
173 }
174
175 return num_tx;
176 }
177
uart_bcm2711_fifo_read(const struct device * dev,uint8_t * rx_data,const int size)178 static int uart_bcm2711_fifo_read(const struct device *dev, uint8_t *rx_data,
179 const int size)
180 {
181 int num_rx = 0U;
182 struct bcm2711_uart_data *uart_data = dev->data;
183
184 while ((size - num_rx) > 0 && bcm2711_mu_lowlevel_can_getc(uart_data->uart_addr)) {
185 /* Receive a character */
186 rx_data[num_rx++] = sys_read32(uart_data->uart_addr + BCM2711_MU_IO) & 0xFF;
187 }
188 return num_rx;
189 }
190
uart_bcm2711_irq_tx_enable(const struct device * dev)191 static void uart_bcm2711_irq_tx_enable(const struct device *dev)
192 {
193 struct bcm2711_uart_data *uart_data = dev->data;
194
195 sys_write32(BCM2711_MU_IER_TX_INTERRUPT, uart_data->uart_addr + BCM2711_MU_IER);
196 }
197
uart_bcm2711_irq_tx_disable(const struct device * dev)198 static void uart_bcm2711_irq_tx_disable(const struct device *dev)
199 {
200 struct bcm2711_uart_data *uart_data = dev->data;
201
202 sys_write32((uint32_t)(~BCM2711_MU_IER_TX_INTERRUPT),
203 uart_data->uart_addr + BCM2711_MU_IER);
204 }
205
uart_bcm2711_irq_tx_ready(const struct device * dev)206 static int uart_bcm2711_irq_tx_ready(const struct device *dev)
207 {
208 struct bcm2711_uart_data *uart_data = dev->data;
209
210 return bcm2711_mu_lowlevel_can_putc(uart_data->uart_addr);
211 }
212
uart_bcm2711_irq_rx_enable(const struct device * dev)213 static void uart_bcm2711_irq_rx_enable(const struct device *dev)
214 {
215 struct bcm2711_uart_data *uart_data = dev->data;
216
217 sys_write32(BCM2711_MU_IER_RX_INTERRUPT, uart_data->uart_addr + BCM2711_MU_IER);
218 }
219
uart_bcm2711_irq_rx_disable(const struct device * dev)220 static void uart_bcm2711_irq_rx_disable(const struct device *dev)
221 {
222 struct bcm2711_uart_data *uart_data = dev->data;
223
224 sys_write32((uint32_t)(~BCM2711_MU_IER_RX_INTERRUPT),
225 uart_data->uart_addr + BCM2711_MU_IER);
226 }
227
uart_bcm2711_irq_rx_ready(const struct device * dev)228 static int uart_bcm2711_irq_rx_ready(const struct device *dev)
229 {
230 struct bcm2711_uart_data *uart_data = dev->data;
231
232 return bcm2711_mu_lowlevel_can_getc(uart_data->uart_addr);
233 }
234
uart_bcm2711_irq_is_pending(const struct device * dev)235 static int uart_bcm2711_irq_is_pending(const struct device *dev)
236 {
237 struct bcm2711_uart_data *uart_data = dev->data;
238
239 return bcm2711_mu_lowlevel_can_getc(uart_data->uart_addr) ||
240 bcm2711_mu_lowlevel_can_putc(uart_data->uart_addr);
241 }
242
uart_bcm2711_irq_update(const struct device * dev)243 static int uart_bcm2711_irq_update(const struct device *dev)
244 {
245 return 1;
246 }
247
uart_bcm2711_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)248 static void uart_bcm2711_irq_callback_set(const struct device *dev,
249 uart_irq_callback_user_data_t cb,
250 void *cb_data)
251 {
252 struct bcm2711_uart_data *data = dev->data;
253
254 data->callback = cb;
255 data->cb_data = cb_data;
256 }
257
258 /**
259 * @brief Interrupt service routine.
260 *
261 * This simply calls the callback function, if one exists.
262 *
263 * Note: imx UART Tx interrupts when ready to send; Rx interrupts when char
264 * received.
265 *
266 * @param arg Argument to ISR.
267 */
uart_isr(const struct device * dev)268 void uart_isr(const struct device *dev)
269 {
270 struct bcm2711_uart_data *data = dev->data;
271
272 if (data->callback) {
273 data->callback(dev, data->cb_data);
274 }
275 }
276 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
277
278 static DEVICE_API(uart, uart_bcm2711_driver_api) = {
279 .poll_in = uart_bcm2711_poll_in,
280 .poll_out = uart_bcm2711_poll_out,
281
282 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
283 .fifo_fill = uart_bcm2711_fifo_fill,
284 .fifo_read = uart_bcm2711_fifo_read,
285 .irq_tx_enable = uart_bcm2711_irq_tx_enable,
286 .irq_tx_disable = uart_bcm2711_irq_tx_disable,
287 .irq_tx_ready = uart_bcm2711_irq_tx_ready,
288 .irq_rx_enable = uart_bcm2711_irq_rx_enable,
289 .irq_rx_disable = uart_bcm2711_irq_rx_disable,
290 .irq_rx_ready = uart_bcm2711_irq_rx_ready,
291 .irq_is_pending = uart_bcm2711_irq_is_pending,
292 .irq_update = uart_bcm2711_irq_update,
293 .irq_callback_set = uart_bcm2711_irq_callback_set,
294 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
295
296 };
297
298 #define UART_DECLARE_CFG(n, IRQ_FUNC_INIT) \
299 static const struct bcm2711_uart_config bcm2711_uart_##n##_config = { \
300 DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)), .baud_rate = DT_INST_PROP(n, current_speed), \
301 .clocks = DT_INST_PROP(n, clock_frequency), IRQ_FUNC_INIT}
302
303 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
304 #define UART_CONFIG_FUNC(n) \
305 static void irq_config_func_##n(const struct device *dev) \
306 { \
307 IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), uart_isr, \
308 DEVICE_DT_INST_GET(n), 0); \
309 irq_enable(DT_INST_IRQN(n)); \
310 }
311 #define UART_IRQ_CFG_FUNC_INIT(n) .irq_config_func = irq_config_func_##n
312 #define UART_INIT_CFG(n) UART_DECLARE_CFG(n, UART_IRQ_CFG_FUNC_INIT(n))
313 #else
314 #define UART_CONFIG_FUNC(n)
315 #define UART_IRQ_CFG_FUNC_INIT
316 #define UART_INIT_CFG(n) UART_DECLARE_CFG(n, UART_IRQ_CFG_FUNC_INIT)
317 #endif
318
319 #define UART_INIT(n) \
320 static struct bcm2711_uart_data bcm2711_uart_##n##_data; \
321 \
322 static const struct bcm2711_uart_config bcm2711_uart_##n##_config; \
323 \
324 DEVICE_DT_INST_DEFINE(n, &uart_bcm2711_init, NULL, &bcm2711_uart_##n##_data, \
325 &bcm2711_uart_##n##_config, PRE_KERNEL_1, \
326 CONFIG_SERIAL_INIT_PRIORITY, &uart_bcm2711_driver_api); \
327 \
328 UART_CONFIG_FUNC(n) \
329 \
330 UART_INIT_CFG(n);
331
332 DT_INST_FOREACH_STATUS_OKAY(UART_INIT)
333
