Searched refs:ADXL362_REG_FIFO_CTL (Results 1 – 3 of 3) sorted by relevance
28 const uint8_t reg_addr_w[3] = {ADXL362_WRITE_REG, ADXL362_REG_FIFO_CTL, fifo_config}; in adxl362_fifo_flush_rtio()38 const uint8_t reg_addr_w2[3] = {ADXL362_WRITE_REG, ADXL362_REG_FIFO_CTL, fifo_config}; in adxl362_fifo_flush_rtio()
51 #define ADXL362_REG_FIFO_CTL 0x28 macro
378 ret = adxl362_set_reg(dev, write_val, ADXL362_REG_FIFO_CTL, 1); in adxl362_fifo_setup()
