Searched refs:ADXL345_FIFO_CTL_REG (Results 1 – 3 of 3) sorted by relevance
83 const uint8_t reg_addr_w2[2] = {ADXL345_FIFO_CTL_REG, fifo_config}; in adxl345_fifo_flush_rtio()93 const uint8_t reg_addr_w3[2] = {ADXL345_FIFO_CTL_REG, fifo_config}; in adxl345_fifo_flush_rtio()
180 ret = adxl345_reg_write_byte(dev, ADXL345_FIFO_CTL_REG, fifo_config); in adxl345_configure_fifo()456 rc = adxl345_reg_write_byte(dev, ADXL345_FIFO_CTL_REG, ADXL345_FIFO_STREAM_MODE); in adxl345_init()
49 #define ADXL345_FIFO_CTL_REG 0x38 macro
