| /Zephyr-Core-3.7.0/tests/lib/cmsis_dsp/transform/src/ |
| D | cf16.pat | 2 0xa963, 0x0, 0x37dd, 0x0, 0x39ca, 0x0, 0x389f, 0x0,
3 0x23a5, 0x0, 0xb69a, 0x0, 0xb9c8, 0x0, 0xb77f, 0x0,
4 0x2638, 0x0, 0x37c1, 0x0, 0x3956, 0x0, 0x3800, 0x0,
5 0x9f32, 0x0, 0xb7f4, 0x0, 0xb9c0, 0x0, 0xb803, 0x0
9 0x2f3e, 0x0, 0xaa72, 0xb333, 0xb07c, 0xc59d, 0xaf3d, 0x20c9,
11 0xb384, 0x0, 0x1b0a, 0x2ec2, 0x2daf, 0xaa77, 0xaebf, 0xa93d,
16 0x2f3e, 0x0, 0xaa72, 0xb333, 0xb07c, 0xc59d, 0xaf3d, 0x20c9,
18 0xb384, 0x0, 0x1b0a, 0x2ec2, 0x2daf, 0xaa77, 0xaebf, 0xa93d,
23 0x2a24, 0x0, 0x3771, 0x0, 0x3a25, 0x0, 0x378e, 0x0,
24 0xabf0, 0x0, 0xb7ba, 0x0, 0xb987, 0x0, 0xb7c1, 0x0,
[all …]
|
| D | cf32.pat | 2 0xbd2c51f4, 0x0, 0x3efba81f, 0x0,
3 0x3f394c4c, 0x0, 0x3f13ead6, 0x0,
4 0x3c74abe0, 0x0, 0xbed34803, 0x0,
5 0xbf38fe14, 0x0, 0xbeefdab0, 0x0,
6 0x3cc6f2eb, 0x0, 0x3ef825ca, 0x0,
7 0x3f2ab374, 0x0, 0x3effffb1, 0x0,
8 0xbbe63a4a, 0x0, 0xbefe8ffa, 0x0,
9 0xbf380fc4, 0x0, 0xbf006c31, 0x0
13 0x3de7b5a7, 0x0, 0xbd4e4efb, 0xbe666912,
17 0xbe708603, 0x0, 0x3b613ac0, 0x3dd8428b,
[all …]
|
| D | cf64.pat | 2 0xbfa58a3e7ce8c268, 0x0,
3 0x3fdf7503d421b8a3, 0x0,
4 0x3fe7298971b2f05d, 0x0,
5 0x3fe27d5ab48bbded, 0x0,
6 0x3f8e957bf3faf458, 0x0,
7 0xbfda690069668b72, 0x0,
8 0xbfe71fc287a1a803, 0x0,
9 0xbfddfb560e6e15ae, 0x0,
10 0x3f98de5d5c60cb98, 0x0,
11 0x3fdf04b94d0d4acb, 0x0,
[all …]
|
| D | rf16.pat | 13 0x0
21 0x0
44 0x0
56 0x0
95 0x0
115 0x0
186 0x0
222 0x0
357 0x0
425 0x0
[all …]
|
| D | rf32.pat | 21 0x0
33 0x0
72 0x0
92 0x0
163 0x0
199 0x0
334 0x0
402 0x0
665 0x0
797 0x0
[all …]
|
| D | rf64.pat | 37 0x0
57 0x0
128 0x0
164 0x0
299 0x0
367 0x0
630 0x0
762 0x0
1281 0x0
1541 0x0
[all …]
|
| /Zephyr-Core-3.7.0/tests/lib/cmsis_dsp/matrix/src/ |
| D | unary_f64.pat | 2443 0x0, 0x0,
2444 0x0, 0x0,
2445 0x0, 0x0,
2446 0x0, 0x0,
2447 0x0, 0x0,
2448 0x0, 0x0,
2449 0x0, 0x0,
2450 0x0, 0x0,
2451 0x3ff0000000000000, 0x0,
2452 0x0, 0x0,
[all …]
|
| D | unary_f32.pat | 1226 0x3e6f4b1f, 0x3f800000, 0x0, 0x0,
1227 0x0, 0x0, 0x0, 0x0,
1228 0x0, 0x0, 0x0, 0x0,
1229 0x0, 0x0, 0x0, 0x0,
1230 0x0, 0x0, 0x3f800000, 0x0,
1231 0x0, 0x0, 0x0, 0x0,
1232 0x0, 0x0, 0x0, 0x0,
1233 0x0, 0x0, 0x0, 0x0,
1234 0x0, 0x0, 0x0, 0x3f800000,
1235 0x0, 0x0, 0x0, 0x0,
[all …]
|
| D | unary_f16.pat | 618 0x337a, 0x3c00, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
619 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
620 0x0, 0x0, 0x3c00, 0x0, 0x0, 0x0, 0x0, 0x0,
621 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
622 0x0, 0x0, 0x0, 0x3c00, 0x0, 0x0, 0x0, 0x0,
623 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
624 0x0, 0x0, 0x0, 0x0, 0x3c00, 0x0, 0x0, 0x0,
625 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
626 0x0, 0x0, 0x0, 0x0, 0x0, 0x3c00, 0x0, 0x0,
627 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
[all …]
|
| /Zephyr-Core-3.7.0/arch/arm64/core/ |
| D | fpu.S | 16 stp q0, q1, [x0, #(16 * 0)]
17 stp q2, q3, [x0, #(16 * 2)]
18 stp q4, q5, [x0, #(16 * 4)]
19 stp q6, q7, [x0, #(16 * 6)]
20 stp q8, q9, [x0, #(16 * 8)]
21 stp q10, q11, [x0, #(16 * 10)]
22 stp q12, q13, [x0, #(16 * 12)]
23 stp q14, q15, [x0, #(16 * 14)]
24 stp q16, q17, [x0, #(16 * 16)]
25 stp q18, q19, [x0, #(16 * 18)]
[all …]
|
| D | userspace.S | 28 mov x3, x0
29 mov x0, #0
34 cmp x0, x1
38 ldrb w5, [x3, x0]
42 add x0, x0, #1
47 mov x0, #0
60 add x1, x1, x0
66 at S1E0R, x0
68 1: at S1E0W, x0
70 2: orr x0, x0, #(MEM_DOMAIN_ALIGN_AND_SIZE - 1)
[all …]
|
| D | reset.S | 44 switch_el x0, 3f, 2f, 1f
49 msr sctlr_el3, x0
62 mrs x0, sctlr_el2
63 bic x0, x0, SCTLR_A_BIT
64 msr sctlr_el2, x0
76 mrs x0, sctlr_el1
77 bic x0, x0, SCTLR_A_BIT
78 msr sctlr_el1, x0
133 ldr x0, =arm64_cpu_boot_params
141 add x4, x0, #BOOT_PARAM_VOTING_OFFSET
[all …]
|
| D | isr_wrapper.S | 36 get_cpu x0
37 ldr w1, [x0, #___cpu_t_nested_OFFSET]
39 str w2, [x0, #___cpu_t_nested_OFFSET]
43 ldr x1, [x0, #___cpu_t_irq_stack_OFFSET]
49 str x1, [x0, #_cpu_offset_to_current_stack_limit]
72 cmp x0, 1019
74 cmp x0, 1023
82 cmp x0, x1
85 stp x0, xzr, [sp, #-16]!
89 add x1, x1, x0, lsl #4 /* table is 16-byte wide */
[all …]
|
| D | vector_table.S | 48 add sp, sp, x0 // sp' = sp + x0
49 sub x0, sp, x0 // x0' = sp' - x0 = sp
57 stp x0, x1, [sp, ___esf_t_x0_x1_OFFSET]
85 mrs x0, sp_el0
86 str x0, [sp, ___esf_t_sp_el0_OFFSET]
89 get_cpu x0
90 ldr x1, [x0, #_cpu_offset_to_safe_exception_stack]
155 z_arm64_enter_exc x0, x1, el1
160 z_arm64_enter_exc x0, x1, el1
173 z_arm64_enter_exc x0, x1, el1
[all …]
|
| D | switch.S | 61 ldrb w2, [x0, #_thread_offset_to_exception_depth]
72 stp x0, x1, [sp, #-16]!
74 ldp x0, x1, [sp], #16
84 ldr x2, [x0, #_thread_offset_to_tls]
93 ldp x19, x20, [x0, #_thread_offset_to_callee_saved_x19_x20]
94 ldp x21, x22, [x0, #_thread_offset_to_callee_saved_x21_x22]
95 ldp x23, x24, [x0, #_thread_offset_to_callee_saved_x23_x24]
96 ldp x25, x26, [x0, #_thread_offset_to_callee_saved_x25_x26]
97 ldp x27, x28, [x0, #_thread_offset_to_callee_saved_x27_x28]
99 ldp x29, x4, [x0, #_thread_offset_to_callee_saved_x29_sp_el0]
[all …]
|
| D | early_mem_funcs.S | 26 tst x0, #0x7
41 str x8, [x0], #8
49 strb w8, [x0], #1
59 orr x8, x1, x0
71 str x8, [x0], #8
80 strb w8, [x0], #1
|
| /Zephyr-Core-3.7.0/tests/lib/cmsis_dsp/filtering/src/ |
| D | misc_f16.pat | 60 0x0, 0x0, 0x0, 0xa168, 0x1f38, 0x2417, 0xa715
64 0x0, 0x0, 0x9fef, 0x9d83, 0x24ce, 0x9c6f, 0xa715
68 0x0, 0xb071, 0x2d6f, 0x328d, 0xb585, 0x9c6f, 0xa715
73 0xb585, 0x9c6f, 0xa715, 0x0, 0x0, 0x0, 0x0
78 0xb23d, 0x353a, 0x2c0a, 0xb585, 0x9c6f, 0xa715, 0x0, 0x0,
79 0x0, 0x0, 0x0, 0x0, 0x0
83 0x0, 0x0, 0x0, 0x0, 0xa168, 0x1f38, 0x2417, 0xa715,
88 0x0, 0x0, 0x0, 0x9fef, 0x9d83, 0x24ce, 0x9c6f, 0xa5fa,
93 0x0, 0x0, 0xb071, 0x2d6f, 0x328d, 0xb585, 0x2cac, 0xa5fa,
99 0xb50a, 0x2cac, 0xa5fa, 0x1e05, 0x0, 0x0, 0x0
[all …]
|
| D | misc_f32.pat | 162 0x0, 0x0, 0x0, 0x3b509f51,
167 0x0, 0x0, 0xbd0f7d56, 0xbc226c2f,
172 0x0, 0x3eb11069, 0x3dc10aa6, 0xbe5acf33,
179 0xbd26293d, 0x3b91a84b, 0xba16913c, 0x0,
180 0x0, 0x0, 0x0
187 0x3b91a84b, 0xba16913c, 0x0, 0x0,
188 0x0, 0x0, 0x0, 0x0,
189 0x0
193 0x0, 0x0, 0x0, 0x0,
199 0x0, 0x0, 0x0, 0xbd0f7d56,
[all …]
|
| /Zephyr-Core-3.7.0/tests/kernel/device/boards/ |
| D | hifive_unmatched.overlay | 19 reg = <0x0 0xE0000000 0x0 0x2000>;
24 reg = <0x0 0xE1000000 0x0 0x2000>;
29 reg = <0x0 0xE2000000 0x0 0x2000>;
34 reg = <0x0 0xE3000000 0x0 0x2000>;
39 reg = <0x0 0xE4000000 0x0 0x2000>;
45 reg = <0x0 0xE5000000 0x0 0x1000>,
46 <0x0 0xE6000000 0x0 0x1000>;
54 reg = <0x0 0xE7000000 0x0 0x2000>;
61 reg = <0x0 0xE8000000 0x0 0x2000>;
|
| /Zephyr-Core-3.7.0/dts/riscv/sifive/ |
| D | riscv64-fu740.dtsi | 110 reg = <0x0 0x1000 0x0 0x1000>;
116 reg = <0x0 0x10000 0x0 0x8000>;
122 reg = <0x0 0x1000000 0x0 0x2000>;
129 reg = <0x0 0x2000000 0x0 0x10000>;
134 reg = <0x0 0x8000000 0x0 0x200000>;
145 reg = <0x0 0x0c000000 0x0 0x04000000>;
154 reg = <0x0 0x10010000 0x0 0x1000>;
163 reg = <0x0 0x10011000 0x0 0x1000>;
172 reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>;
183 reg = <0x0 0x10041000 0x0 0x1000>;
[all …]
|
| /Zephyr-Core-3.7.0/soc/neorv32/ |
| D | reset.S | 17 lui x0, 0
20 csrw mstatus, x0
21 csrw mie, x0
25 csrw mcounteren, x0
33 csrw mcycle, x0
34 csrw mcycleh, x0
35 csrw minstret, x0
36 csrw minstreth, x0
56 1: sw x0, 0(x8)
|
| /Zephyr-Core-3.7.0/dts/common/broadcom/ |
| D | viper-common.dtsi | 48 reg = <0x0 0x4e100000 0x0 0x2100>,
49 <0x0 0x50000000 0x0 0x8000000>,
50 <0x4 0x0 0x0 0x8000000>;
59 reg = <0x0 0x4e100800 0x0 0x2100>,
60 <0x0 0x4f000000 0x0 0x200000>,
61 <0x0 0x4f200000 0x0 0x10000>;
|
| /Zephyr-Core-3.7.0/dts/riscv/starfive/ |
| D | starfive_jh7100_beagle_v.dtsi | 81 reg = <0x0 0x80000000 0x2 0x0>;
101 reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>;
107 reg = <0x0 0x1808000 0x0 0x8000>;
113 reg = <0x0 0x1820000 0x0 0x8000>;
121 reg = <0x0 0x2000000 0x0 0x10000>;
131 reg = <0x0 0x0c000000 0x0 0x04000000>;
140 reg = <0x0 0x12440000 0x0 0x10000>;
153 reg = <0x0 0x12430000 0x0 0x10000>;
166 reg = <0x0 0x11880000 0x0 0x10000>;
179 reg = <0x0 0x11870000 0x0 0x10000>;
|
| /Zephyr-Core-3.7.0/tests/lib/shared_multi_heap/boards/ |
| D | qemu_cortex_a53.overlay | 14 reg = <0x0 0x42000000 0x0 0x1000>;
21 reg = <0x0 0x43000000 0x0 0x2000>;
28 reg = <0x0 0x45000000 0x0 0x1000>;
34 reg = <0x0 0x44000000 0x0 0x3000>;
|
| /Zephyr-Core-3.7.0/boards/sifive/hifive_unmatched/ |
| D | hifive_unmatched.dts | 20 reg = <0x0 0x80000000 0x4 0x00000000>;
32 reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x2000000>;
|
