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/Zephyr-Core-3.7.0/soc/nxp/s32/s32k3/
Dpmc.c15 #define PMC_LVSC_HVDAF(v) FIELD_PREP(PMC_LVSC_HVDAF_MASK, (v)) argument
17 #define PMC_LVSC_HVDBF(v) FIELD_PREP(PMC_LVSC_HVDBF_MASK, (v)) argument
19 #define PMC_LVSC_HVD25F(v) FIELD_PREP(PMC_LVSC_HVD25F_MASK, (v)) argument
21 #define PMC_LVSC_HVD11F(v) FIELD_PREP(PMC_LVSC_HVD11F_MASK, (v)) argument
23 #define PMC_LVSC_LVD5AF(v) FIELD_PREP(PMC_LVSC_LVD5AF_MASK, (v)) argument
25 #define PMC_LVSC_LVD15F(v) FIELD_PREP(PMC_LVSC_LVD15F_MASK, (v)) argument
27 #define PMC_LVSC_HVDAS(v) FIELD_PREP(PMC_LVSC_HVDAS_MASK, (v)) argument
29 #define PMC_LVSC_HVDBS(v) FIELD_PREP(PMC_LVSC_HVDBS_MASK, (v)) argument
31 #define PMC_LVSC_HVD25S(v) FIELD_PREP(PMC_LVSC_HVD25S_MASK, (v)) argument
33 #define PMC_LVSC_HVD11S(v) FIELD_PREP(PMC_LVSC_HVD11S_MASK, (v)) argument
[all …]
Dpinctrl_soc.h17 #define SIUL2_MSCR_SSS(v) FIELD_PREP(SIUL2_MSCR_SSS_MASK, (v)) argument
19 #define SIUL2_MSCR_SMC(v) FIELD_PREP(SIUL2_MSCR_SMC_MASK, (v)) argument
21 #define SIUL2_MSCR_IFE(v) FIELD_PREP(SIUL2_MSCR_IFE_MASK, (v)) argument
23 #define SIUL2_MSCR_DSE(v) FIELD_PREP(SIUL2_MSCR_DSE_MASK, (v)) argument
25 #define SIUL2_MSCR_PUS(v) FIELD_PREP(SIUL2_MSCR_PUS_MASK, (v)) argument
27 #define SIUL2_MSCR_PUE(v) FIELD_PREP(SIUL2_MSCR_PUE_MASK, (v)) argument
29 #define SIUL2_MSCR_SRC(v) FIELD_PREP(SIUL2_MSCR_SRC_MASK, (v)) argument
31 #define SIUL2_MSCR_PKE(v) FIELD_PREP(SIUL2_MSCR_PKE_MASK, (v)) argument
33 #define SIUL2_MSCR_INV(v) FIELD_PREP(SIUL2_MSCR_INV_MASK, (v)) argument
35 #define SIUL2_MSCR_IBE(v) FIELD_PREP(SIUL2_MSCR_IBE_MASK, (v)) argument
[all …]
/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_stm32_ll_common.h18 #define z_pllm(v) LL_RCC_PLLM_DIV_ ## v argument
19 #define pllm(v) z_pllm(v) argument
21 #define z_pllp(v) LL_RCC_PLLP_DIV_ ## v argument
22 #define pllp(v) z_pllp(v) argument
24 #define z_pllq(v) LL_RCC_PLLQ_DIV_ ## v argument
25 #define pllq(v) z_pllq(v) argument
27 #define z_pllr(v) LL_RCC_PLLR_DIV_ ## v argument
28 #define pllr(v) z_pllr(v) argument
30 #define z_plli2s_m(v) LL_RCC_PLLI2SM_DIV_ ## v argument
31 #define plli2sm(v) z_plli2s_m(v) argument
[all …]
Dclock_stm32l0_l1.c22 #define z_pll_mul(v) LL_RCC_PLL_MUL_ ## v argument
23 #define pll_mul(v) z_pll_mul(v) argument
25 #define z_pll_div(v) LL_RCC_PLL_DIV_ ## v argument
26 #define pll_div(v) z_pll_div(v) argument
/Zephyr-Core-3.7.0/soc/nxp/s32/s32ze/
Dpinctrl_soc.h17 #define SIUL2_MSCR_SSS(v) FIELD_PREP(SIUL2_MSCR_SSS_MASK, (v)) argument
19 #define SIUL2_MSCR_SMC(v) FIELD_PREP(SIUL2_MSCR_SMC_MASK, (v)) argument
21 #define SIUL2_MSCR_TRC(v) FIELD_PREP(SIUL2_MSCR_TRC_MASK, (v)) argument
23 #define SIUL2_MSCR_RCVR(v) FIELD_PREP(SIUL2_MSCR_RCVR_MASK, (v)) argument
25 #define SIUL2_MSCR_CREF(v) FIELD_PREP(SIUL2_MSCR_CREF_MASK, (v)) argument
27 #define SIUL2_MSCR_PUS(v) FIELD_PREP(SIUL2_MSCR_PUS_MASK, (v)) argument
29 #define SIUL2_MSCR_PUE(v) FIELD_PREP(SIUL2_MSCR_PUE_MASK, (v)) argument
31 #define SIUL2_MSCR_SRE(v) FIELD_PREP(SIUL2_MSCR_SRE_MASK, (v)) argument
33 #define SIUL2_MSCR_RXCB(v) FIELD_PREP(SIUL2_MSCR_RXCB_MASK, (v)) argument
35 #define SIUL2_MSCR_IBE(v) FIELD_PREP(SIUL2_MSCR_IBE_MASK, (v)) argument
[all …]
/Zephyr-Core-3.7.0/soc/nxp/s32/common/
Dmc_me.c17 #define MC_ME_CTL_KEY_KEY(v) FIELD_PREP(MC_ME_CTL_KEY_KEY_MASK, (v)) argument
21 #define MC_ME_MODE_CONF_DEST_RST(v) FIELD_PREP(MC_ME_MODE_CONF_DEST_RST_MASK, (v)) argument
23 #define MC_ME_MODE_CONF_FUNC_RST(v) FIELD_PREP(MC_ME_MODE_CONF_FUNC_RST_MASK, (v)) argument
25 #define MC_ME_MODE_CONF_STANDBY(v) FIELD_PREP(MC_ME_MODE_CONF_STANDBY_MASK, (v)) argument
29 #define MC_ME_MODE_UPD_MODE_UPD(v) FIELD_PREP(MC_ME_MODE_UPD_MODE_UPD_MASK, (v)) argument
33 #define MC_ME_MODE_STAT_PREV_MODE(v) FIELD_PREP(MC_ME_MODE_STAT_PREV_MODE_MASK, (v)) argument
37 #define MC_ME_MAIN_COREID_CIDX(v) FIELD_PREP(MC_ME_MAIN_COREID_CIDX_MASK, (v)) argument
39 #define MC_ME_MAIN_COREID_PIDX(v) FIELD_PREP(MC_ME_MAIN_COREID_PIDX_MASK, (v)) argument
43 #define MC_ME_PRTN_PCONF_PCE(v) FIELD_PREP(MC_ME_PRTN_PCONF_PCE_MASK, (v)) argument
47 #define MC_ME_PRTN_PUPD_PCUD(v) FIELD_PREP(MC_ME_PRTN_PUPD_PCUD_MASK, (v)) argument
[all …]
Dmc_rgm.c15 #define MC_RGM_DES_F_POR(v) FIELD_PREP(MC_RGM_DES_F_POR_MASK, (v)) argument
19 #define MC_RGM_FES_F_EXR(v) FIELD_PREP(MC_RGM_FES_F_EXR_MASK, (v)) argument
27 #define MC_RGM_FREC_FREC(v) FIELD_PREP(MC_RGM_FREC_FREC_MASK, (v)) argument
31 #define MC_RGM_FRET_FRET(v) FIELD_PREP(MC_RGM_FRET_FRET_MASK, (v)) argument
35 #define MC_RGM_DRET_DRET(v) FIELD_PREP(MC_RGM_DRET_DRET_MASK, (v)) argument
39 #define MC_RGM_ERCTRL_ERASSERT(v) FIELD_PREP(MC_RGM_ERCTRL_ERASSERT_MASK, (v)) argument
43 #define MC_RGM_RDSS_DES_RES(v) FIELD_PREP(MC_RGM_RDSS_DES_RES_MASK, (v)) argument
45 #define MC_RGM_RDSS_FES_RES(v) FIELD_PREP(MC_RGM_RDSS_FES_RES_MASK, (v)) argument
49 #define MC_RGM_FRENTC_FRET_EN(v) FIELD_PREP(MC_RGM_FRENTC_FRET_EN_MASK, (v)) argument
51 #define MC_RGM_FRENTC_FRET_TIMEOUT(v) FIELD_PREP(MC_RGM_FRENTC_FRET_TIMEOUT_MASK, (v)) argument
[all …]
/Zephyr-Core-3.7.0/scripts/coccinelle/
Dunsigned_suffix.cocci13 … unsigned short, unsigned int, uint8_t, uint16_t, uint32_t, uint64_t, u8_t, u16_t, u32_t, u64_t} v;
19 v = C@p
21 v == C@p
23 v != C@p
25 v <= C@p
27 v >= C@p
29 v += C@p
31 v -= C@p
33 v * C@p
35 v / C@p
[all …]
Dsame_identifier.cocci16 identifier t, v;
19 struct t *v@p;
21 struct t v@p;
23 union t v@p;
28 v << common_case.v;
32 msg = "WARNING: Violation to rule 5.7 (Tag name should be unique) tag: {}".format(v)
33 if t == v:
38 identifier v;
42 T v@p;
44 T *v@p;
[all …]
Dreserved_names.cocci16 identifier t, v;
21 struct t *v@p;
23 struct t v@p;
25 union t v@p;
27 T v@p;
29 T *v@p;
31 struct t *v@p = E;
33 struct t v@p = E;
35 union t v@p = E;
37 T v@p = E;
[all …]
Dboolean.cocci16 identifier function, v;
22 T1 function(P1, T2 v, P2) {...}
24 T1 function(P1, T2 *v, P2) {...}
29 v << rule1_base.v;
36 identifier rule1_base.v;
40 while (v@p) {...}
42 if (v@p) {...}
53 identifier v;
56 T v;
61 v << rule2_base.v;
[all …]
/Zephyr-Core-3.7.0/tests/crypto/mbedtls/src/
Dmbedtls.c148 int v, suites_tested = 0, suites_failed = 0; in ZTEST_USER() local
175 v = 1; in ZTEST_USER()
185 if (mbedtls_md2_self_test(v) != 0) { in ZTEST_USER()
192 if (mbedtls_md4_self_test(v) != 0) { in ZTEST_USER()
199 if (mbedtls_md5_self_test(v) != 0) { in ZTEST_USER()
206 if (mbedtls_ripemd160_self_test(v) != 0) { in ZTEST_USER()
213 if (mbedtls_sha1_self_test(v) != 0) { in ZTEST_USER()
220 if (mbedtls_sha256_self_test(v) != 0) { in ZTEST_USER()
227 if (mbedtls_sha512_self_test(v) != 0) { in ZTEST_USER()
234 if (mbedtls_arc4_self_test(v) != 0) { in ZTEST_USER()
[all …]
/Zephyr-Core-3.7.0/drivers/sensor/tdk/icm42605/
Dicm42605_setup.c151 uint8_t v; in icm42605_sensor_init() local
153 result = inv_spi_read(&cfg->spi, REG_WHO_AM_I, &v, 1); in icm42605_sensor_init()
159 LOG_DBG("WHO AM I : 0x%X", v); in icm42605_sensor_init()
161 result = inv_spi_read(&cfg->spi, REG_DEVICE_CONFIG, &v, 1); in icm42605_sensor_init()
168 v |= BIT_SOFT_RESET; in icm42605_sensor_init()
170 result = inv_spi_single_write(&cfg->spi, REG_DEVICE_CONFIG, &v); in icm42605_sensor_init()
180 v = BIT_GYRO_AFSR_MODE_HFS | BIT_ACCEL_AFSR_MODE_HFS | BIT_CLK_SEL_PLL; in icm42605_sensor_init()
182 result = inv_spi_single_write(&cfg->spi, REG_INTF_CONFIG1, &v); in icm42605_sensor_init()
189 v = BIT_EN_DREG_FIFO_D2A | in icm42605_sensor_init()
193 result = inv_spi_single_write(&cfg->spi, REG_TMST_CONFIG, &v); in icm42605_sensor_init()
[all …]
/Zephyr-Core-3.7.0/drivers/charger/
Dcharger_bq24190.c73 uint8_t v; in bq24190_charger_get_charge_type() local
78 ret = i2c_reg_read_byte_dt(&config->i2c, BQ24190_REG_POC, &v); in bq24190_charger_get_charge_type()
83 v = FIELD_GET(BQ24190_REG_POC_CHG_CONFIG_MASK, v); in bq24190_charger_get_charge_type()
85 if (!v) { in bq24190_charger_get_charge_type()
88 ret = i2c_reg_read_byte_dt(&config->i2c, BQ24190_REG_CCC, &v); in bq24190_charger_get_charge_type()
93 v = FIELD_GET(BQ24190_REG_CCC_FORCE_20PCT_MASK, v); in bq24190_charger_get_charge_type()
95 if (v) { in bq24190_charger_get_charge_type()
108 uint8_t v; in bq24190_charger_get_health() local
111 ret = i2c_reg_read_byte_dt(&config->i2c, BQ24190_REG_F, &v); in bq24190_charger_get_health()
116 if (v & BQ24190_REG_F_NTC_FAULT_MASK) { in bq24190_charger_get_health()
[all …]
/Zephyr-Core-3.7.0/drivers/edac/
Dibecc.h144 #define INTER_CHAN_DDR_TYPE(v) BITFIELD(v, 2, 0) argument
146 #define INTER_CHAN_ECHM(v) BITFIELD(v, 3, 3) argument
148 #define INTER_CHAN_CH_L_MAP(v) BITFIELD(v, 4, 4) argument
150 #define INTER_CHAN_CH_S_SIZE BITFIELD(v, 19, 12)
155 #define DIMM_L_MAP(v) BITFIELD(v, 0, 0) argument
160 #define DIMM_L_SIZE(v) (BITFIELD(v, 6, 0) << 29) argument
162 #define DIMM_L_WIDTH(v) BITFIELD(v, 8, 7) argument
164 #define DIMM_S_SIZE(v) (BITFIELD(v, 22, 16) << 29) argument
166 #define DIMM_S_WIDTH(v) BITFIELD(v, 25, 24) argument
/Zephyr-Core-3.7.0/include/zephyr/arch/xtensa/
Darch_inlines.h24 ({uint32_t v; \
25 __asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
26 v; })
34 #define XTENSA_WSR(sr, v) \ argument
36 __asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
47 ({uint32_t v; \
48 __asm__ volatile ("rur." ur " %0" : "=a"(v)); \
49 v; })
57 #define XTENSA_WUR(ur, v) \ argument
59 __asm__ volatile ("wur." ur " %0" : : "r"(v)); \
/Zephyr-Core-3.7.0/include/zephyr/arch/arc/asm-compat/
Dasm-macro-32-bit-mwdt.h47 .macro ADDR, d, s, v
48 add\&$suffix d, s, v
51 .macro ADD2R, d, s, v
52 add2\&$suffix d, s, v
55 .macro ADD3R, d, s, v
56 add3 d, s, v
59 .macro SUBR, d, s, v
60 sub d, s, v
63 .macro BMSKNR, d, s, v
64 bmskn d, s, v
[all …]
Dasm-macro-64-bit-mwdt.h47 .macro ADDR, d, s, v
48 addl\&$suffix d, s, v
51 .macro ADD2R, d, s, v
52 add2l\&$suffix d, s, v
55 .macro ADD3R, d, s, v
56 add3l d, s, v
59 .macro SUBR, d, s, v
60 subl d, s, v
63 .macro BMSKNR, d, s, v
64 bmsknl d, s, v
[all …]
Dasm-macro-32-bit-gnu.h50 .macro ADDR\cc d, s, v
51 add\cc \d, \s, \v
56 .macro ADD2R\cc d, s, v
57 add2\cc \d, \s, \v
61 .macro ADD3R d, s, v
62 add3 \d, \s, \v
65 .macro SUBR d, s, v
66 sub \d, \s, \v
69 .macro BMSKNR d, s, v
70 bmskn \d, \s, \v
[all …]
Dasm-macro-64-bit-gnu.h62 .macro ADDR\cc d, s, v
63 addl\cc \d, \s, \v
68 .macro ADD2R\cc d, s, v
69 add2l\cc \d, \s, \v
73 .macro ADD3R d, s, v
74 add3l \d, \s, \v
77 .macro SUBR d, s, v
78 subl \d, \s, \v
81 .macro BMSKNR d, s, v
82 bmsknl \d, \s, \v
[all …]
/Zephyr-Core-3.7.0/scripts/pylib/twister/twisterlib/
Dconfig_parser.py105 v = value.strip()
107 return v
122 vs = v.split()
140 vs = v.split()
174 for k, v in self.common.items():
178 {"CONF_FILE", "OVERLAY_CONFIG", "DTC_OVERLAY_FILE"}, v
182 d[k] = copy.copy(v)
184 for k, v in self.scenarios[name].items():
187 extracted_testsuite, v = extract_fields_from_arg_list(
188 {"CONF_FILE", "OVERLAY_CONFIG", "DTC_OVERLAY_FILE"}, v
[all …]
/Zephyr-Core-3.7.0/drivers/watchdog/
Dwdt_nxp_s32.c22 #define SWT_CR_WEN(v) FIELD_PREP(SWT_CR_WEN_MASK, (v)) argument
24 #define SWT_CR_FRZ(v) FIELD_PREP(SWT_CR_FRZ_MASK, (v)) argument
26 #define SWT_CR_STP(v) FIELD_PREP(SWT_CR_STP_MASK, (v)) argument
28 #define SWT_CR_SLK(v) FIELD_PREP(SWT_CR_SLK_MASK, (v)) argument
30 #define SWT_CR_HLK(v) FIELD_PREP(SWT_CR_HLK_MASK, (v)) argument
32 #define SWT_CR_ITR(v) FIELD_PREP(SWT_CR_ITR_MASK, (v)) argument
34 #define SWT_CR_WND(v) FIELD_PREP(SWT_CR_WND_MASK, (v)) argument
36 #define SWT_CR_RIA(v) FIELD_PREP(SWT_CR_RIA_MASK, (v)) argument
38 #define SWT_CR_SMD(v) FIELD_PREP(SWT_CR_SMD_MASK, (v)) argument
40 #define SWT_CR_MAP(v) FIELD_PREP(SWT_CR_MAP_MASK, (v)) argument
[all …]
/Zephyr-Core-3.7.0/samples/subsys/sip_svc/
DREADME.rst39 Got response of transaction id 0x00 and voltage is 0.846878v
40 Got response of transaction id 0x01 and voltage is 0.858170v
41 Got response of transaction id 0x02 and voltage is 0.860168v
42 Got response of transaction id 0x03 and voltage is 0.846832v
43 Got response of transaction id 0x04 and voltage is 0.858337v
44 Got response of transaction id 0x05 and voltage is 0.871704v
45 Got response of transaction id 0x06 and voltage is 0.859421v
46 Got response of transaction id 0x07 and voltage is 0.857254v
47 Got response of transaction id 0x08 and voltage is 0.858429v
48 Got response of transaction id 0x09 and voltage is 0.859879v
[all …]
/Zephyr-Core-3.7.0/scripts/dts/python-devicetree/src/devicetree/
Dgrutils.py81 for v in self.__nodes:
82 self.__tarjan_index[v] = None
101 def _tarjan_root(self, v): argument
104 if self.__tarjan_index.get(v) is not None:
107 self.__tarjan_index[v] = self.__tarjan_low_link[v] = self.__index
109 self.__stack.append(v)
110 source = v
114 … self.__tarjan_low_link[v] = min(self.__tarjan_low_link[v], self.__tarjan_low_link[target])
116 … self.__tarjan_low_link[v] = min(self.__tarjan_low_link[v], self.__tarjan_low_link[target])
118 if self.__tarjan_low_link[v] == self.__tarjan_index[v]:
[all …]
/Zephyr-Core-3.7.0/subsys/logging/
Dlog_output_syst.c78 struct stp_writer_data *p, mipi_syst_u8 v) in stp_write_d4() argument
80 stp_write_putNibble(systh, p, v); in stp_write_d4()
84 struct stp_writer_data *p, mipi_syst_u8 v) in stp_write_payload8() argument
86 stp_write_d4(systh, p, v); in stp_write_payload8()
87 stp_write_d4(systh, p, v>>4); in stp_write_payload8()
91 struct stp_writer_data *p, mipi_syst_u16 v) in stp_write_payload16() argument
93 stp_write_payload8(systh, p, (mipi_syst_u8)v); in stp_write_payload16()
94 stp_write_payload8(systh, p, (mipi_syst_u8)(v>>8)); in stp_write_payload16()
98 struct stp_writer_data *p, mipi_syst_u32 v) in stp_write_payload32() argument
100 stp_write_payload16(systh, p, (mipi_syst_u16)v); in stp_write_payload32()
[all …]

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