| /Zephyr-Core-3.7.0/soc/openisa/rv32m1/ |
| D | soc_irq.S | 36 sw t1, 0x00(t0)
55 sw t0, __soc_esf_t_lpstart0_OFFSET(a0)
56 sw t1, __soc_esf_t_lpend0_OFFSET(a0)
57 sw t2, __soc_esf_t_lpcount0_OFFSET(a0)
61 sw t0, __soc_esf_t_lpstart1_OFFSET(a0)
62 sw t1, __soc_esf_t_lpend1_OFFSET(a0)
63 sw t2, __soc_esf_t_lpcount1_OFFSET(a0)
|
| D | wdog.S | 49 sw t2, WDOG_CNT_OFFSET(t1)
55 sw t2, WDOG_CS_OFFSET(t1)
59 sw t2, WDOG_TOVAL_OFFSET(t1)
|
| /Zephyr-Core-3.7.0/soc/andestech/ae350/ |
| D | soc_irq.S | 28 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
31 sw t1, __soc_esf_t_ucode_OFFSET(a0)
|
| /Zephyr-Core-3.7.0/soc/telink/tlsr/tlsr951x/ |
| D | soc_irq.S | 32 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
35 sw t1, __soc_esf_t_ucode_OFFSET(a0)
|
| D | start.S | 51 sw t0, 0(t2)
62 sw t0, 0(t2)
74 sw t0, 0(t2)
|
| /Zephyr-Core-3.7.0/arch/riscv/core/ |
| D | userspace.S | 29 sw a5, 0(a2) # Init error value to 0
50 sw a4, 0(a2)
|
| D | asm_macros.inc | 21 /* register-wide load/store based on lw/sw (XLEN = 32) */
28 sw \rs, \mem
|
| D | reset.S | 71 sw t2, 0x00(t0)
|
| D | fpu.S | 59 sw t0, __z_riscv_fp_context_t_fcsr_OFFSET(a0)
|
| D | isr.S | 471 sw t2, ___cpu_t_nested_OFFSET(s0)
524 sw t1, 0(sp)
587 sw t2, ___cpu_t_nested_OFFSET(s0)
649 sw t2, ___cpu_t_nested_OFFSET(s0)
|
| /Zephyr-Core-3.7.0/modules/lvgl/ |
| D | CMakeLists.txt | 80 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_arc.c
81 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_blend.c
82 ${LVGL_DIR}/src/draw/sw/lv_draw_sw.c
83 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_dither.c
84 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_gradient.c
85 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_img.c
86 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_layer.c
87 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_letter.c
88 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_line.c
89 ${LVGL_DIR}/src/draw/sw/lv_draw_sw_polygon.c
[all …]
|
| /Zephyr-Core-3.7.0/drivers/clock_control/ |
| D | clock_control_numaker_scc.c | 110 #define LOG_OSC_SW(osc, sw) \ argument
111 if (sw == NUMAKER_SCC_CLKSW_ENABLE) { \
113 } else if (sw == NUMAKER_SCC_CLKSW_DISABLE) { \
|
| /Zephyr-Core-3.7.0/arch/xtensa/include/ |
| D | xtensa_mmu_priv.h | 67 #define XTENSA_MMU_PTE(paddr, ring, sw, attr) \ argument
70 (((sw) << XTENSA_MMU_PTE_SW_SHIFT) & XTENSA_MMU_PTE_SW_MASK) | \
82 #define XTENSA_MMU_PTE_SW_SET(pte, sw) \ argument
83 (((pte) & ~XTENSA_MMU_PTE_SW_MASK) | (sw << XTENSA_MMU_PTE_SW_SHIFT))
|
| /Zephyr-Core-3.7.0/soc/nordic/common/vpr/ |
| D | soc_context.S | 14 sw t0, __soc_esf_t_minttresh_OFFSET(a0)
|
| /Zephyr-Core-3.7.0/soc/espressif/esp32c3/ |
| D | soc_irq.S | 15 sw ra, 0x00(sp)
|
| /Zephyr-Core-3.7.0/dts/common/nordic/ |
| D | nrf_common.dtsi | 39 sw_pwm: sw-pwm {
40 compatible = "nordic,nrf-sw-pwm";
|
| /Zephyr-Core-3.7.0/samples/boards/nrf/mesh/onoff-app/src/ |
| D | main.c | 268 static struct switch_data sw; variable
433 k_timer_start(&sw.button_timer, K_SECONDS(1), K_NO_WAIT); in button_pressed()
443 sw.sw_num = pin_to_sw(pin_pos); in button_pressed()
459 k_work_submit(&sw.button_work); in button_cnt_timer()
586 k_work_init(&sw.button_work, button_pressed_worker); in main()
589 k_timer_init(&sw.button_timer, button_cnt_timer, NULL); in main()
|
| /Zephyr-Core-3.7.0/soc/espressif/esp32c6/ |
| D | soc_irq.S | 21 sw ra, 0x00(sp)
|
| /Zephyr-Core-3.7.0/arch/mips/core/ |
| D | reset.S | 41 sw t2, 0(t0)
|
| /Zephyr-Core-3.7.0/drivers/interrupt_controller/ |
| D | intc_nuclei_eclic.S | 40 sw ra, 0(sp)
|
| /Zephyr-Core-3.7.0/include/zephyr/arch/mips/ |
| D | arch.h | 26 #define OP_STOREREG sw
|
| /Zephyr-Core-3.7.0/soc/neorv32/ |
| D | reset.S | 56 1: sw x0, 0(x8)
|
| /Zephyr-Core-3.7.0/tests/subsys/mem_mgmt/mem_attr_heap/boards/ |
| D | qemu_cortex_m3.overlay | 3 #include <zephyr/dt-bindings/memory-attr/memory-attr-sw.h>
|
| /Zephyr-Core-3.7.0/boards/native/nrf_bsim/ |
| D | nrf5340bsim_nrf5340_cpunet.dts | 50 /delete-node/ sw-pwm;
|
| D | nrf54l15bsim_nrf54l15_cpuapp.dts | 24 /delete-node/ sw-pwm;
|
