Searched refs:s6 (Results 1 – 10 of 10) sorted by relevance
| /Zephyr-Core-3.7.0/include/zephyr/arch/mips/ |
| D | thread.h | 40 unsigned long s6; /* saved register */ member
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| /Zephyr-Core-3.7.0/arch/mips/include/mips/ |
| D | regdef.h | 48 #define s6 $22 macro
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| /Zephyr-Core-3.7.0/include/zephyr/arch/riscv/ |
| D | thread.h | 40 unsigned long s6; /* saved register */ member
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| /Zephyr-Core-3.7.0/arch/mips/core/offsets/ |
| D | offsets.c | 22 GEN_OFFSET_SYM(_callee_saved_t, s6);
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| /Zephyr-Core-3.7.0/scripts/build/ |
| D | check_init_priorities_test.py | 123 s6 = mock.Mock()
124 s6.name = "__init_end"
125 s6.entry.st_value = 0x66
127 sts.iter_symbols.return_value = [s0, s1, s2, s3, s4, s5, s6]
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| /Zephyr-Core-3.7.0/arch/riscv/core/ |
| D | switch.S | 25 RV_I( op s6, _thread_offset_to_s6(reg) );\
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| D | fatal.c | 92 LOG_ERR(" s0: " PR_REG " s6: " PR_REG, csf->s0, csf->s6); in z_riscv_fatal_error_csf()
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| D | isr.S | 53 RV_I( sr s6, ___callee_saved_t_s6_OFFSET(sp) );\
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| /Zephyr-Core-3.7.0/arch/mips/core/ |
| D | isr.S | 29 op s6, THREAD_O(s6)(reg) ;\
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| /Zephyr-Core-3.7.0/arch/riscv/core/offsets/ |
| D | offsets.c | 40 GEN_OFFSET_SYM(_callee_saved_t, s6);
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