Searched refs:s5 (Results 1 – 11 of 11) sorted by relevance
| /Zephyr-Core-3.7.0/include/zephyr/arch/mips/ |
| D | thread.h | 39 unsigned long s5; /* saved register */ member
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| /Zephyr-Core-3.7.0/arch/mips/include/mips/ |
| D | regdef.h | 47 #define s5 $21 macro
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| /Zephyr-Core-3.7.0/include/zephyr/arch/riscv/ |
| D | thread.h | 39 unsigned long s5; /* saved register */ member
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| /Zephyr-Core-3.7.0/arch/mips/core/offsets/ |
| D | offsets.c | 21 GEN_OFFSET_SYM(_callee_saved_t, s5);
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| /Zephyr-Core-3.7.0/scripts/build/ |
| D | check_init_priorities_test.py | 119 s5 = mock.Mock()
120 s5.name = "__init_SMP_start"
121 s5.entry.st_value = 0x55
127 sts.iter_symbols.return_value = [s0, s1, s2, s3, s4, s5, s6]
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| /Zephyr-Core-3.7.0/arch/riscv/core/ |
| D | switch.S | 24 RV_I( op s5, _thread_offset_to_s5(reg) );\
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| D | fatal.c | 97 LOG_ERR(" s5: " PR_REG " s11: " PR_REG, csf->s5, csf->s11); in z_riscv_fatal_error_csf()
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| D | isr.S | 52 RV_I( sr s5, ___callee_saved_t_s5_OFFSET(sp) );\
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| /Zephyr-Core-3.7.0/arch/mips/core/ |
| D | isr.S | 28 op s5, THREAD_O(s5)(reg) ;\
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| /Zephyr-Core-3.7.0/arch/riscv/core/offsets/ |
| D | offsets.c | 39 GEN_OFFSET_SYM(_callee_saved_t, s5);
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| /Zephyr-Core-3.7.0/dts/arm/nuvoton/npcx/ |
| D | npcx-espi-vws-map.dtsi | 46 vw-slp-s5 {
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