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Searched refs:reg_base (Results 1 – 25 of 46) sorted by relevance

12

/Zephyr-Core-3.7.0/drivers/sdhc/
Dsdhc_cdns_ll.c81 data = sys_read32(cdns_params.reg_base + SDHC_CDNS_SRS09); in sdhc_cdns_busy()
89 if (!WAIT_FOR((((sys_read32(cdns_params.reg_base + SDHC_CDNS_SRS09)) in sdhc_cdns_card_present()
103 (cdns_params.reg_base + SDHC_CDNS_SRS10)); in sdhc_cdns_vol_reset()
110 (cdns_params.reg_base + SDHC_CDNS_SRS10)); in sdhc_cdns_vol_reset()
183 ret = sdhc_cdns_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04, in sdhc_cdns_program_phy_reg()
184 cdns_params.combophy + PHY_DQS_TIMING_REG, cdns_params.reg_base in sdhc_cdns_program_phy_reg()
200 ret = sdhc_cdns_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04, in sdhc_cdns_program_phy_reg()
201 cdns_params.combophy + PHY_GATE_LPBK_CTRL_REG, cdns_params.reg_base in sdhc_cdns_program_phy_reg()
214 ret = sdhc_cdns_write_phy_reg(cdns_params.reg_base + SDHC_CDNS_HRS04, in sdhc_cdns_program_phy_reg()
215 cdns_params.combophy + PHY_DLL_MASTER_CTRL_REG, cdns_params.reg_base in sdhc_cdns_program_phy_reg()
[all …]
/Zephyr-Core-3.7.0/drivers/i2c/
Di2c_dw.c60 uint32_t reg_base = get_regs(dev); in i2c_dw_enable_idma() local
63 write_dma_cr(DW_IC_DMA_ENABLE, reg_base); in i2c_dw_enable_idma()
64 reg = sys_read32(reg_base + DW_IC_REG_DMA_CR); in i2c_dw_enable_idma()
66 reg = read_dma_cr(reg_base); in i2c_dw_enable_idma()
68 write_dma_cr(reg, reg_base); in i2c_dw_enable_idma()
69 reg = sys_read32(reg_base + DW_IC_REG_DMA_CR); in i2c_dw_enable_idma()
92 uint32_t reg_base = get_regs(dev); in i2c_dw_set_fifo_th() local
94 write_tdlr(fifo_depth, reg_base); in i2c_dw_set_fifo_th()
95 write_rdlr(fifo_depth - 1, reg_base); in i2c_dw_set_fifo_th()
209 uint32_t reg_base = get_regs(dev); in i2c_dw_data_ask() local
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Di2c_mcux_lpi2c_rtio.c42 DEVICE_MMIO_NAMED_ROM(reg_base);
56 DEVICE_MMIO_NAMED_RAM(reg_base);
83 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_do_configure()
140 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_msg_start()
215 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_complete()
279 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_isr()
293 DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP); in mcux_lpi2c_init()
295 base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_init()
353 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
Di2c_mcux_lpi2c.c44 DEVICE_MMIO_NAMED_ROM(reg_base);
61 DEVICE_MMIO_NAMED_RAM(reg_base);
81 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_configure()
157 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_transfer()
320 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_slave_irq_handler()
415 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_target_register()
463 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_target_unregister()
481 LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_isr()
504 DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP); in mcux_lpi2c_init()
506 base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_lpi2c_init()
[all …]
/Zephyr-Core-3.7.0/drivers/serial/
Duart_xlnx_ps.c180 static void xlnx_ps_disable_uart(uintptr_t reg_base) in xlnx_ps_disable_uart() argument
182 uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_disable_uart()
187 sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_disable_uart()
204 static void xlnx_ps_enable_uart(uintptr_t reg_base) in xlnx_ps_enable_uart() argument
206 uint32_t reg_val = sys_read32(reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_enable_uart()
211 sys_write32(reg_val, reg_base + XUARTPS_CR_OFFSET); in xlnx_ps_enable_uart()
233 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in set_baudrate() local
268 sys_write32(divisor, reg_base + XUARTPS_BAUDDIV_OFFSET); in set_baudrate()
269 sys_write32(generator, reg_base + XUARTPS_BAUDGEN_OFFSET); in set_baudrate()
291 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in uart_xlnx_ps_init() local
[all …]
/Zephyr-Core-3.7.0/drivers/spi/
Dspi_npcx_spip.c33 struct spip_reg *reg_base; member
47 struct spip_reg *const reg_base = config->reg_base; in spi_npcx_spip_configure() local
84 reg_base->SPIP_CTL1 &= ~BIT(NPCX_SPIP_CTL1_MOD); in spi_npcx_spip_configure()
86 reg_base->SPIP_CTL1 |= BIT(NPCX_SPIP_CTL1_MOD); in spi_npcx_spip_configure()
116 reg_base->SPIP_CTL1 |= BIT(NPCX_SPIP_CTL1_SCIDL); in spi_npcx_spip_configure()
118 reg_base->SPIP_CTL1 &= ~BIT(NPCX_SPIP_CTL1_SCIDL); in spi_npcx_spip_configure()
122 reg_base->SPIP_CTL1 |= BIT(NPCX_SPIP_CTL1_SCM); in spi_npcx_spip_configure()
124 reg_base->SPIP_CTL1 &= ~BIT(NPCX_SPIP_CTL1_SCM); in spi_npcx_spip_configure()
137 SET_FIELD(reg_base->SPIP_CTL1, NPCX_SPIP_CTL1_SCDV, prescaler_divider); in spi_npcx_spip_configure()
177 struct spip_reg *const reg_base = config->reg_base; in spi_npcx_spip_xfer_frame() local
[all …]
/Zephyr-Core-3.7.0/drivers/counter/
Dcounter_dw_timer.c87 uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(timer_dev, timer_mmio); in counter_dw_timer_irq_handler() local
93 sys_read32(reg_base + EOI_OFST); in counter_dw_timer_irq_handler()
103 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT); in counter_dw_timer_irq_handler()
117 uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, timer_mmio); in counter_dw_timer_start() local
120 sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT); in counter_dw_timer_start()
123 sys_clear_bit(reg_base + CONTROLREG_OFST, TIMER_MODE_BIT); in counter_dw_timer_start()
124 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_INTR_MASK_BIT); in counter_dw_timer_start()
125 sys_write32(FREE_RUNNING_MODE_VAL, reg_base + LOADCOUNT_OFST); in counter_dw_timer_start()
128 sys_set_bit(reg_base + CONTROLREG_OFST, TIMER_CONTROL_ENABLE_BIT); in counter_dw_timer_start()
134 uintptr_t reg_base = DEVICE_MMIO_NAMED_GET(dev, timer_mmio); in counter_dw_timer_disable() local
[all …]
/Zephyr-Core-3.7.0/drivers/gpio/
Dgpio_altera_pio.c24 uintptr_t reg_base; member
44 uintptr_t reg_base = cfg->reg_base; in gpio_pin_direction() local
57 addr = reg_base + ALTERA_AVALON_PIO_DIRECTION_OFFSET; in gpio_pin_direction()
75 uintptr_t reg_base = cfg->reg_base; in gpio_altera_configure() local
89 addr = reg_base + ALTERA_AVALON_PIO_DIRECTION_OFFSET; in gpio_altera_configure()
109 uintptr_t reg_base = cfg->reg_base; in gpio_altera_port_get_raw() local
112 addr = reg_base + ALTERA_AVALON_PIO_DATA_OFFSET; in gpio_altera_port_get_raw()
129 uintptr_t reg_base = cfg->reg_base; in gpio_altera_port_set_bits_raw() local
144 addr = reg_base + ALTERA_AVALON_PIO_SET_BITS; in gpio_altera_port_set_bits_raw()
147 addr = reg_base + ALTERA_AVALON_PIO_DATA_OFFSET; in gpio_altera_port_set_bits_raw()
[all …]
Dgpio_mcux_rgpio.c33 DEVICE_MMIO_NAMED_ROM(reg_base);
45 DEVICE_MMIO_NAMED_RAM(reg_base);
54 RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_rgpio_configure()
129 RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_rgpio_port_get_raw()
140 RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_rgpio_port_set_masked_raw()
150 RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_rgpio_port_set_bits_raw()
160 RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_rgpio_port_clear_bits_raw()
170 RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_rgpio_port_toggle_bits()
182 RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_rgpio_pin_interrupt_configure()
227 RGPIO_Type *base = (RGPIO_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base); in mcux_rgpio_port_isr()
[all …]
Dgpio_brcmstb.c24 DEVICE_MMIO_NAMED_ROM(reg_base);
31 DEVICE_MMIO_NAMED_RAM(reg_base);
122 DEVICE_MMIO_NAMED_MAP(port, reg_base, K_MEM_CACHE_NONE); in gpio_brcmstb_init()
123 data->base = DEVICE_MMIO_NAMED_GET(port, reg_base) + config->offset; in gpio_brcmstb_init()
133 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_INST_PARENT(n)), \
Dgpio_intel.c99 DEVICE_MMIO_NAMED_ROM(reg_base);
112 DEVICE_MMIO_NAMED_RAM(reg_base);
128 #define GPIO_REG_BASE_GET(dev) DEVICE_MMIO_NAMED_GET(dev, reg_base)
146 #define GPIO_REG_BASE_GET(dev) GPIO_REG_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base))
173 return GPIO_PAD_BASE(DEVICE_MMIO_NAMED_GET(dev, reg_base)); in pad_base()
578 device_map(&data->reg_base, res.reg_base, res.len, K_MEM_CACHE_NONE); in gpio_intel_acpi_enum()
643 device_map(&data->reg_base, in gpio_intel_dts_init()
644 cfg->reg_base.phys_addr & ~0xFFU, in gpio_intel_dts_init()
645 cfg->reg_base.size, in gpio_intel_dts_init()
648 DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE); in gpio_intel_dts_init()
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/Zephyr-Core-3.7.0/soc/intel/alder_lake/
Dsoc_gpio.h29 #define GPIO_REG_BASE(reg_base) \ argument
30 (reg_base & ~PAD_BASE_ADDR_MASK)
32 #define GPIO_PAD_BASE(reg_base) \ argument
33 (reg_base & PAD_BASE_ADDR_MASK)
/Zephyr-Core-3.7.0/soc/intel/elkhart_lake/
Dsoc_gpio.h29 #define GPIO_REG_BASE(reg_base) \ argument
30 (reg_base & ~PAD_BASE_ADDR_MASK)
32 #define GPIO_PAD_BASE(reg_base) \ argument
33 (reg_base & PAD_BASE_ADDR_MASK)
/Zephyr-Core-3.7.0/soc/intel/raptor_lake/
Dsoc_gpio.h36 #define GPIO_REG_BASE(reg_base) \ argument
37 (reg_base & ~PAD_BASE_ADDR_MASK)
39 #define GPIO_PAD_BASE(reg_base) \ argument
40 (reg_base & PAD_BASE_ADDR_MASK)
/Zephyr-Core-3.7.0/drivers/flash/
Dflash_cadence_qspi_nor_ll.c23 return (sys_read32(cad_params->reg_base + CAD_QSPI_CFG) & CAD_QSPI_CFG_IDLE) >> 31; in cad_qspi_idle()
37 sys_clear_bits(cad_params->reg_base + CAD_QSPI_CFG, ~CAD_QSPI_CFG_BAUDDIV_MSK); in cad_qspi_set_baudrate_div()
39 sys_set_bits(cad_params->reg_base + CAD_QSPI_CFG, CAD_QSPI_CFG_BAUDDIV(div)); in cad_qspi_set_baudrate_div()
55 cad_params->reg_base + CAD_QSPI_DEVSZ); in cad_qspi_configure_dev_size()
72 cad_params->reg_base + CAD_QSPI_DEVRD); in cad_qspi_set_read_config()
88 cad_params->reg_base + CAD_QSPI_DEVWR); in cad_qspi_set_write_config()
102 uint32_t cfg = sys_read32(cad_params->reg_base + CAD_QSPI_CFG); in cad_qspi_timing_config()
107 sys_write32(cfg, cad_params->reg_base + CAD_QSPI_CFG); in cad_qspi_timing_config()
111 cad_params->reg_base + CAD_QSPI_DELAY); in cad_qspi_timing_config()
126 sys_write32((sys_read32(cad_params->reg_base + CAD_QSPI_CFG) & CAD_QSPI_CFG_CS_MSK) | in cad_qspi_stig_cmd_helper()
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/Zephyr-Core-3.7.0/include/zephyr/acpi/
Dacpi.h18 #define ACPI_MMIO_GET(res) (res)->reg_base[0].mmio
19 #define ACPI_IO_GET(res) (res)->reg_base[0].port
20 #define ACPI_RESOURCE_SIZE_GET(res) (res)->reg_base[0].length
21 #define ACPI_RESOURCE_TYPE_GET(res) (res)->reg_base[0].type
23 #define ACPI_MULTI_MMIO_GET(res, idx) (res)->reg_base[idx].mmio
24 #define ACPI_MULTI_IO_GET(res, idx) (res)->reg_base[idx].port
25 #define ACPI_MULTI_RESOURCE_SIZE_GET(res, idx) (res)->reg_base[idx].length
26 #define ACPI_MULTI_RESOURCE_TYPE_GET(res, idx) (res)->reg_base[idx].type
80 struct acpi_reg_base *reg_base; member
/Zephyr-Core-3.7.0/drivers/watchdog/
Dwdt_dw.c57 uintptr_t reg_base = DEVICE_MMIO_GET(dev); in dw_wdt_setup() local
67 dw_wdt_response_mode_set((uint32_t)reg_base, !!dev_data->callback); in dw_wdt_setup()
70 return dw_wdt_configure((uint32_t)reg_base, dev_data->config); in dw_wdt_setup()
77 uintptr_t reg_base = DEVICE_MMIO_GET(dev); local
101 return dw_wdt_calc_period((uint32_t)reg_base, dev_data->clk_freq, config,
107 uintptr_t reg_base = DEVICE_MMIO_GET(dev); local
114 dw_wdt_counter_restart((uint32_t)reg_base);
162 uintptr_t reg_base = DEVICE_MMIO_GET(dev); local
188 ret = dw_wdt_probe((uint32_t)reg_base, dev_config->reset_pulse_length);
204 dw_wdt_enable((uint32_t)reg_base);
[all …]
Dwdt_opentitan.c90 volatile uintptr_t reg_base = dev_cfg->regs; in ot_aontimer_install_timeout() local
115 if (!sys_read32(reg_base + OT_REG_WDOG_REGWEN_OFFSET)) { in ot_aontimer_install_timeout()
121 if (sys_read32(reg_base + OT_REG_WDOG_CTRL_OFFSET) & BIT(0)) { in ot_aontimer_install_timeout()
137 sys_write32((uint32_t) bark_thold, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET); in ot_aontimer_install_timeout()
138 sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET); in ot_aontimer_install_timeout()
147 sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET); in ot_aontimer_install_timeout()
149 sys_write32(UINT32_MAX, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET); in ot_aontimer_install_timeout()
154 sys_write32(UINT32_MAX, reg_base + OT_REG_WDOG_BARK_THOLD_OFFSET); in ot_aontimer_install_timeout()
155 sys_write32((uint32_t) bite_thold, reg_base + OT_REG_WDOG_BITE_THOLD_OFFSET); in ot_aontimer_install_timeout()
/Zephyr-Core-3.7.0/drivers/pwm/
Dpwm_intel_blinky.c26 DEVICE_MMIO_NAMED_ROM(reg_base);
33 DEVICE_MMIO_NAMED_RAM(reg_base);
78 sys_write32(val, rt->reg_base + cfg->reg_offset); in bk_intel_set_cycles()
107 device_map(&runtime->reg_base, in bk_intel_init()
108 config->reg_base.phys_addr & ~0xFFU, in bk_intel_init()
109 config->reg_base.size, in bk_intel_init()
117 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
/Zephyr-Core-3.7.0/soc/intel/common/
Dsoc_gpio.c50 struct acpi_reg_base reg_base[CONFIG_ACPI_MMIO_ENTRIES_MAX]; in soc_acpi_gpio_resource_get() local
58 mmio_res.mmio_max = ARRAY_SIZE(reg_base); in soc_acpi_gpio_resource_get()
59 mmio_res.reg_base = reg_base; in soc_acpi_gpio_resource_get()
86 res->reg_base = ACPI_MMIO_GET(&mmio_res) & (~0x0FFFFFF); in soc_acpi_gpio_resource_get()
87 res->reg_base += field_val[0]; in soc_acpi_gpio_resource_get()
/Zephyr-Core-3.7.0/tests/lib/acpi/integration/src/
Dmain.c53 struct acpi_reg_base reg_base[CONFIG_ACPI_MMIO_ENTRIES_MAX]; in ZTEST() local
62 mmio_res.mmio_max = ARRAY_SIZE(reg_base); in ZTEST()
63 mmio_res.reg_base = reg_base; in ZTEST()
/Zephyr-Core-3.7.0/drivers/misc/timeaware_gpio/
Dtimeaware_gpio_intel.c53 DEVICE_MMIO_NAMED_ROM(reg_base);
59 DEVICE_MMIO_NAMED_RAM(reg_base);
64 return DEVICE_MMIO_NAMED_GET(dev, reg_base); in regs()
205 device_map(&rt->reg_base, in tgpio_init()
206 cfg->reg_base.phys_addr & ~0xFFU, in tgpio_init()
207 cfg->reg_base.size, in tgpio_init()
216 DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)), \
/Zephyr-Core-3.7.0/drivers/reset/
Dreset_npcx.c33 struct swrst_reg *reg_base; member
39 struct swrst_reg *const reg = config->reg_base; in reset_npcx_line_toggle()
74 .reg_base = (struct swrst_reg *)DT_INST_REG_ADDR(0),
/Zephyr-Core-3.7.0/drivers/peci/
Dpeci_ite_it8xxx2.c118 static void peci_it8xxx2_init_vtts(struct peci_it8xxx2_regs *reg_base, in peci_it8xxx2_init_vtts() argument
121 reg_base->PADCTLR = (reg_base->PADCTLR & PECI_DVIE) | vol_opt; in peci_it8xxx2_init_vtts()
124 static void peci_it8xxx2_rst_status(struct peci_it8xxx2_regs *reg_base) in peci_it8xxx2_rst_status() argument
126 reg_base->HOSTAR = HOSTAR_RST_ANYBIT; in peci_it8xxx2_rst_status()
129 static int peci_it8xxx2_check_host_busy(struct peci_it8xxx2_regs *reg_base) in peci_it8xxx2_check_host_busy() argument
131 return (reg_base->HOSTAR & HOBY) ? (-EBUSY) : 0; in peci_it8xxx2_check_host_busy()
/Zephyr-Core-3.7.0/lib/acpi/
Dacpi.c491 struct acpi_reg_base *reg_base = mmio_res->reg_base; in acpi_device_mmio_get() local
502 reg_base[mmio_cnt].type = ACPI_RES_TYPE_IO; in acpi_device_mmio_get()
503 reg_base[mmio_cnt].port = (uint32_t)res->Data.Io.Minimum; in acpi_device_mmio_get()
504 reg_base[mmio_cnt++].length = res->Data.Io.AddressLength; in acpi_device_mmio_get()
508 reg_base[mmio_cnt].type = ACPI_RES_TYPE_IO; in acpi_device_mmio_get()
509 reg_base[mmio_cnt].port = (uint32_t)res->Data.FixedIo.Address; in acpi_device_mmio_get()
510 reg_base[mmio_cnt++].length = res->Data.FixedIo.AddressLength; in acpi_device_mmio_get()
514 reg_base[mmio_cnt].type = ACPI_RES_TYPE_MEM; in acpi_device_mmio_get()
515 reg_base[mmio_cnt].mmio = (uintptr_t)res->Data.Memory24.Minimum; in acpi_device_mmio_get()
516 reg_base[mmio_cnt++].length = res->Data.Memory24.AddressLength; in acpi_device_mmio_get()
[all …]

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