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Searched refs:read_sysreg (Results 1 – 9 of 9) sorted by relevance

/Zephyr-Core-3.7.0/soc/brcm/bcmvk/viper/a72/
Dplat_core.c25 reg = read_sysreg(CORTEX_A72_L2ACTLR_EL1); in z_arm64_el3_plat_init()
/Zephyr-Core-3.7.0/include/zephyr/arch/arm64/
Dlib_helpers.h17 #define read_sysreg(reg) \ macro
40 return read_sysreg(reg); \
Dcache.h62 ctr_el0 = read_sysreg(CTR_EL0); in arch_dcache_line_size_get()
Dcpu.h84 #define GET_MPIDR() read_sysreg(mpidr_el1)
/Zephyr-Core-3.7.0/include/zephyr/arch/arm/cortex_a_r/
Dlib_helpers.h100 #define read_sysreg(reg) read_##reg() macro
Dcpu.h97 #define GET_MPIDR() read_sysreg(mpidr)
/Zephyr-Core-3.7.0/arch/arm64/core/
Dreset.c98 reg = read_sysreg(ICC_SRE_EL3); in z_arm64_el3_init()
/Zephyr-Core-3.7.0/arch/arm/core/cortex_a_r/
Dcache.c40 val = read_sysreg(ctr); in arch_dcache_line_size_get()
/Zephyr-Core-3.7.0/drivers/interrupt_controller/
Dintc_gicv3.c243 intid = read_sysreg(ICC_IAR1_EL1); in arm_gic_get_active()
414 icc_sre = read_sysreg(ICC_SRE_EL1); in gicv3_cpuif_init()
420 icc_sre = read_sysreg(ICC_SRE_EL1); in gicv3_cpuif_init()