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Searched refs:r3 (Results 1 – 25 of 192) sorted by relevance

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/Zephyr-Core-3.7.0/arch/arc/core/
Dswitch.S67 _st32_huge_offset _CAUSE_COOP, r2, _thread_offset_to_relinquish_cause, r3
73 LRR r3, [_ARC_V2_STATUS32]
74 PUSHR r3
78 lr r3, [_ARC_V2_SEC_STAT]
80 mov_s r3, 0
82 push_s r3
92 _disable_stack_checking r3
98 breq r3, _CAUSE_RIRQ, _switch_return_from_rirq
100 breq r3, _CAUSE_FIRQ, _switch_return_from_firq
110 pop_s r3 /* pop SEC_STAT */
[all …]
Dfault_s.S135 lr r3,[_ARC_V2_ERSEC_STAT]
136 btst r3, 31
137 bset.nz r3, r3, _ARC_V2_SEC_STAT_IRM_BIT
138 bclr.z r3, r3, _ARC_V2_SEC_STAT_IRM_BIT
139 sflag r3
151 LRR r3, [_ARC_V2_STATUS32]
152 ANDR r3, r3, (~(_ARC_V2_STATUS32_AE | _ARC_V2_STATUS32_RB(7)))
153 kflag r3
162 mov_s r3, (1 << (ARC_N_IRQ_START_LEVEL - 1))
164 MOVR r3, (1 << (CONFIG_NUM_IRQ_PRIO_LEVELS - 1))
[all …]
Disr_wrapper.S226 mov_s r3, _firq_exit
231 mov_s r3, _rirq_exit
235 mov.z r3, _firq_exit
237 mov.nz r3, _rirq_exit
242 MOVR r3, _rirq_exit
252 breq r3, 0, _skip_pm_save_idle_exit
266 PUSHR r3
292 lr r3, [_ARC_V2_AUX_IRQ_HINT]
293 brne r3, r0, irq_hint_handled
325 POPR r3
[all …]
Dreset.S106 lr r3, [_ARC_V2_D_CACHE_BUILD]
107 and.f r3, r3, 0xff
136 lr r3, [_ARC_V2_MPU_BUILD]
137 lsr_s r3, r3, 8
138 and r3, r3, 0xff
143 brge r2, r3, done_mpu_regions_reset
Dregular_irq.S253 lr r3, [_ARC_V2_SEC_STAT]
254 push_s r3
273 breq r3, _CAUSE_RIRQ, _rirq_switch_from_rirq
275 breq r3, _CAUSE_FIRQ, _rirq_switch_from_firq
Dthread_entry_wrapper.S32 POPR r3
45 MOVR sp, r3
Duserspace.S19 mov_s r3, 0
63 pop_s r3
75 st.aw r3, [r5, -4]
110 push_s r3
248 mov_s r3, -1
249 st_s r3, [sp, 0]
/Zephyr-Core-3.7.0/arch/arm/core/cortex_a_r/
Dexc_exit.S87 add r3, sp, #___fpu_sf_t_fpscr_OFFSET
88 ldm r3, {r1, r2}
94 mov r3, sp
95 vldmia r3!, {s0-s15}
97 vldmia r3!, {d16-d31}
144 get_cpu r3
145 ldr r0, [r3, #___cpu_t_nested_OFFSET]
149 ldr r1, [r3, #___cpu_t_current_OFFSET]
164 pop {r2, r3}
165 add sp, sp, r3
[all …]
Dswitch.S45 ldrb r3, [r2, #_cpu_offset_to_exc_depth]
46 strb r3, [r1, #_thread_offset_to_exception_depth]
49 ldrb r3, [r0, #_thread_offset_to_exception_depth]
50 strb r3, [r2, #_cpu_offset_to_exc_depth]
63 ldr r3, [r0, #_thread_offset_to_tls]
69 mcr 15, 0, r3, c13, c0, 2
134 ldr r3, [r2, #___cpu_t_nested_OFFSET]
135 add r3, r3, #1
136 str r3, [r2, #___cpu_t_nested_OFFSET]
139 cmp r3, #1
Dswap_helper.S93 vmrs r3, fpscr
94 stm r0, {r3, ip}
114 ldr r3, =_kernel
115 ldr r2, [r3, #_kernel_offset_to_ready_q_cache]
141 movs r3, #0
142 str r3, [r2, #_thread_offset_to_basepri]
158 mov r3, #FPEXC_EN
159 vmsr fpexc, r3
165 mov r3, #0
166 vmsr fpexc, r3
[all …]
Disr_wrapper.S87 push {r0-r3, r12, lr}
139 and r3, sp, #4
140 sub sp, sp, r3
141 push {r2, r3}
211 ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */
212 blx r3 /* call ISR */
311 ldm r1!,{r0,r3} /* arg in r0, ISR in r3 */
317 blx r3 /* call ISR */
Dmacro_priv.inc31 * Store r0-r3, r12, lr into the stack to construct an exception
36 stmdb sp, {r0-r3, r12, lr}^
/Zephyr-Core-3.7.0/arch/arm/core/
Duserspace.S111 push {r1,r2,r3,lr}
139 pop {r0,r3}
142 ldr r0, [r3]
143 ldr r3, [r3, #4]
144 mov ip, r3
146 push {r0,r3}
183 pop {r1,r2,r3,r4}
188 pop {r1,r2,r3,lr}
253 push {r0, r1, r2, r3}
260 mrs r3, CONTROL
[all …]
/Zephyr-Core-3.7.0/arch/arm/core/cortex_m/
Dswap_helper.S90 mov r3, r8
96 stmea r0!, {r3-r7}
141 ldmia r0!, {r3-r7}
143 mov r8, r3
161 movs.n r3, #0
162 vmsr fpscr, r3
175 mrs r3, CONTROL
176 bic r3, #_CONTROL_FPCA_Msk
177 msr CONTROL, r3
278 movs r3, #0x1
[all …]
Dfault_s.S89 mov r3, r11
91 push {r2, r3}
92 mov r3, r9
94 push {r2, r3}
99 mov r3, sp /* pointer to _callee_saved_t */
Dcoredump.c19 uint32_t r3; member
69 arch_blk.r.r3 = esf->basic.r3; in arch_coredump_info_dump()
/Zephyr-Core-3.7.0/soc/nxp/lpc/lpc54xxx/gcc/
Dstartup_LPC54114_cm4.S55 ldrh r3, [r6, #18] /* Mask for CPU ID bits */
56 cmp r3, r2 /* Core ID matches M4 identifier */
64 ldr r3, [r0] /* r3 = SYSCON co-processor CPU control status */
66 ands r3, r3, r5 /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */
71 eors r3, r3, r4 /* r4 = (Bit 0: 0 = master, 1 = slave) */
/Zephyr-Core-3.7.0/arch/nios2/core/
Dswap.S100 ldw r3, _thread_offset_to_key(r2)
114 andi r3, r3, NIOS2_STATUS_PIE_MSK
115 beq r3, zero, no_unlock
116 rdctl r3, status
117 ori r3, r3, NIOS2_STATUS_PIE_MSK
118 wrctl status, r3
122 wrctl status, r3
131 stw r3, 4(sp)
137 ldw r3, 4(sp)
Dcrt0.S112 movhi r3, 0xaaaa
113 ori r3, r3, 0xaaaa
117 stw r3, (r1)
/Zephyr-Core-3.7.0/include/zephyr/arch/arm/
Dsyscall.h47 register uint32_t r3 __asm__("r3") = arg4; in arch_syscall_invoke6()
53 : "=r"(ret), "=r"(r1), "=r"(r2), "=r"(r3) in arch_syscall_invoke6()
55 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke6()
70 register uint32_t r3 __asm__("r3") = arg4; in arch_syscall_invoke5()
75 : "=r"(ret), "=r"(r1), "=r"(r2), "=r"(r3) in arch_syscall_invoke5()
77 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke5()
91 register uint32_t r3 __asm__("r3") = arg4; in arch_syscall_invoke4()
95 : "=r"(ret), "=r"(r1), "=r"(r2), "=r"(r3) in arch_syscall_invoke4()
97 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke4()
/Zephyr-Core-3.7.0/arch/arc/include/
Dswap_macros.h198 STR r3, sp, ___isf_t_r3_OFFSET
259 LDR r3, sp, ___isf_t_r3_OFFSET
284 ld r3, [r2, _thread_offset_to_k_stack_base]
285 sr r3, [_ARC_V2_S_KSTACK_BASE]
286 ld r3, [r2, _thread_offset_to_k_stack_top]
287 sr r3, [_ARC_V2_S_KSTACK_TOP]
289 ld r3, [r2, _thread_offset_to_u_stack_base]
290 sr r3, [_ARC_V2_S_USTACK_BASE]
291 ld r3, [r2, _thread_offset_to_u_stack_top]
292 sr r3, [_ARC_V2_S_USTACK_TOP]
[all …]
/Zephyr-Core-3.7.0/soc/nxp/s32/s32k3/
Ds32k3xx_startup.S48 movs r3, 0
51 stm r1!, {r0,r3}
65 stm r1!, {r0,r3}
78 stm r1!, {r0,r3}
/Zephyr-Core-3.7.0/include/zephyr/arch/arm64/
Dsyscall.h47 register uint64_t r3 __asm__("x3") = arg4; in arch_syscall_invoke6()
55 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke6()
70 register uint64_t r3 __asm__("x3") = arg4; in arch_syscall_invoke5()
77 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke5()
91 register uint64_t r3 __asm__("x3") = arg4; in arch_syscall_invoke4()
97 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke4()
/Zephyr-Core-3.7.0/include/zephyr/arch/arc/
Dsyscall.h48 register uint32_t r3 __asm__("r3") = arg4; in arch_syscall_invoke6()
59 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke6()
73 register uint32_t r3 __asm__("r3") = arg4; in arch_syscall_invoke5()
83 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke5()
96 register uint32_t r3 __asm__("r3") = arg4; in arch_syscall_invoke4()
105 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in arch_syscall_invoke4()
/Zephyr-Core-3.7.0/include/zephyr/arch/arc/v2/secureshield/
Darc_secure.h60 register uint32_t r3 __asm__("r3") = arg4; in _arc_s_call_invoke6()
71 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in _arc_s_call_invoke6()
83 register uint32_t r3 __asm__("r3") = arg4; in _arc_s_call_invoke5()
93 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in _arc_s_call_invoke5()
105 register uint32_t r3 __asm__("r3") = arg4; in _arc_s_call_invoke4()
114 "r" (ret), "r" (r1), "r" (r2), "r" (r3), in _arc_s_call_invoke4()

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