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Searched refs:pllc_reg (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_agilex_ll.c57 uint32_t pllm_reg, pllc_reg, pllc_div, pllglob_reg; in get_clk_freq() local
64 pllc_reg = CLKMGR_MAINPLL + main_pllc; in get_clk_freq()
69 pllc_reg = CLKMGR_PERPLL + per_pllc; in get_clk_freq()
80 pllc_div = mmio_read_32(pllc_reg) & 0x7ff; in get_clk_freq()
Dclock_control_agilex5_ll.c85 uint32_t pllm_reg, pllc_reg, pllc_div, pllglob_reg; in get_clk_freq() local
92 pllc_reg = clock_agilex5_ll.mainpll_addr + main_pllc; in get_clk_freq()
98 pllc_reg = clock_agilex5_ll.peripll_addr + per_pllc; in get_clk_freq()
111 pllc_div = CLKMGR_PLLC_DIV(sys_read32(pllc_reg)); in get_clk_freq()