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Searched refs:pcfg (Results 1 – 25 of 248) sorted by relevance

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/Zephyr-latest/drivers/serial/
Duart_realtek_rts5912.c25 const struct pinctrl_dev_config *pcfg; member
48 rc = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT); in rts5912_uart_init()
60 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
/Zephyr-latest/drivers/gpio/
Dgpio_silabs_siwx91x.c66 const struct gpio_siwx91x_common_config *pcfg = parent->config; in gpio_siwx91x_pin_configure() local
116 pcfg->reg->PIN_CONFIG[(cfg->port << 4) + pin].GPIO_CONFIG_REG_b.MODE = 0; in gpio_siwx91x_pin_configure()
143 const struct gpio_siwx91x_common_config *pcfg = parent->config; in gpio_siwx91x_port_set_masked() local
146 pcfg->reg->PORT_CONFIG[cfg->port].PORT_LOAD_REG = in gpio_siwx91x_port_set_masked()
147 (pcfg->reg->PORT_CONFIG[cfg->port].PORT_LOAD_REG & ~mask) | (value & mask); in gpio_siwx91x_port_set_masked()
229 const struct gpio_siwx91x_common_config *pcfg = parent->config; in gpio_siwx91x_interrupt_configure() local
244 pcfg->reg->INTR[i].GPIO_INTR_CTRL_b.MASK = 1; in gpio_siwx91x_interrupt_configure()
303 const struct gpio_siwx91x_common_config *pcfg = parent->config; in gpio_siwx91x_isr() local
310 uint32_t pending = pcfg->reg->INTR[i].GPIO_INTR_STATUS_b.INTERRUPT_STATUS; in gpio_siwx91x_isr()
314 pcfg->reg->INTR[i].GPIO_INTR_STATUS_b.INTERRUPT_STATUS = 1; in gpio_siwx91x_isr()
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Dgpio_sy1xx.c58 pinctrl_soc_pin_t pcfg = { in sy1xx_gpio_driver_configure() local
68 pcfg.cfg |= BIT(SY1XX_PAD_PULL_UP_OFFS); in sy1xx_gpio_driver_configure()
71 pcfg.cfg |= BIT(SY1XX_PAD_PULL_DOWN_OFFS); in sy1xx_gpio_driver_configure()
75 pcfg.cfg |= BIT(SY1XX_PAD_DIR_OFFS); in sy1xx_gpio_driver_configure()
85 pcfg.cfg |= BIT(SY1XX_PAD_TRISTATE_OFFS); in sy1xx_gpio_driver_configure()
93 int32_t ret = pinctrl_configure_pins(&pcfg, 1, PINCTRL_STATE_DEFAULT); in sy1xx_gpio_driver_configure()
/Zephyr-latest/drivers/memc/
Dmemc_stm32.c36 const struct pinctrl_dev_config *pcfg; member
47 r = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in memc_stm32_init()
97 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
Dmemc_sam_smc.c30 const struct pinctrl_dev_config *pcfg; member
43 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in memc_smc_init()
100 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
/Zephyr-latest/drivers/i2c/
Di2c_nrfx_twim_common.c38 (void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in i2c_nrfx_twim_recover_bus()
111 (void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in twim_nrfx_pm_action()
116 (void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP); in twim_nrfx_pm_action()
131 (void)pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP); in i2c_nrfx_twim_common_init()
Di2c_b91.c22 const struct pinctrl_dev_config *pcfg; member
140 status = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in i2c_b91_init()
170 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
/Zephyr-latest/tests/drivers/pinctrl/nrf/src/
Dmain.c13 static const struct pinctrl_dev_config *pcfg = PINCTRL_DT_DEV_CONFIG_GET(TEST_DEVICE); variable
19 zassert_equal(pcfg->reg, 0x0U); in ZTEST()
20 zassert_equal(pcfg->state_cnt, 1U); in ZTEST()
22 scfg = &pcfg->states[0]; in ZTEST()
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_mco.c22 const struct pinctrl_dev_config *pcfg; member
64 return pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in stm32_mco_init()
72 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
Dclock_control_ambiq.c21 const struct pinctrl_dev_config *pcfg; member
109 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in ambiq_clock_configure()
133 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n)}; \
/Zephyr-latest/drivers/ps2/
Dps2_npcx_channel.c35 const struct pinctrl_dev_config *pcfg; member
90 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in ps2_npcx_channel_init()
115 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
/Zephyr-latest/drivers/pwm/
Dpwm_ene_kb1200.c17 const struct pinctrl_dev_config *pcfg; member
103 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in pwm_kb1200_init()
116 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
Dpwm_xmc4xxx_ccu4.c26 const struct pinctrl_dev_config *pcfg; member
48 return pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in pwm_xmc4xxx_ccu4_init()
106 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
Dpwm_b91.c15 const struct pinctrl_dev_config *pcfg; member
49 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in pwm_b91_init()
123 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
Dpwm_sam.c35 const struct pinctrl_dev_config *pcfg; member
117 retval = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in sam_pwm_init()
137 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
Dpwm_mchp_xec_bbled.c124 const struct pinctrl_dev_config *pcfg; member
289 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT); in pwm_bbled_xec_pm_action()
311 ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_SLEEP); in pwm_bbled_xec_pm_action()
333 int ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in pwm_bbled_xec_init()
363 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
Dpwm_cc13xx_cc26xx_timer.c42 const struct pinctrl_dev_config *pcfg; member
180 pinctrl_soc_pin_t pin = config->pcfg->states[0].pins[0]; in init_pwm()
202 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in init_pwm()
246 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
/Zephyr-latest/drivers/input/
Dinput_xec_kbd.c32 const struct pinctrl_dev_config *pcfg; member
157 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in xec_kbd_pm_action()
172 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP); in xec_kbd_pm_action()
193 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in xec_kbd_init()
241 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
/Zephyr-latest/drivers/comparator/
Dcomparator_renesas_ra.c25 const struct pinctrl_dev_config *pcfg; member
29 const struct pinctrl_dev_config *pcfg; member
145 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in acmphs_renesas_ra_global_init()
161 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in acmphs_renesas_ra_init()
199 .pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST(0, renesas_ra_acmphs_global)),
252 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
/Zephyr-latest/drivers/sensor/ene_tach_kb1200/
Dtach_ene_kb1200.c21 const struct pinctrl_dev_config *pcfg; member
115 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in tach_kb1200_init()
136 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
/Zephyr-latest/drivers/sensor/qdec_sam/
Dqdec_sam.c30 const struct pinctrl_dev_config *pcfg; member
102 retval = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT); in qdec_sam_initialize()
129 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
/Zephyr-latest/drivers/dac/
Ddac_gd32.c40 const struct pinctrl_dev_config *pcfg; member
157 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in dac_gd32_init()
179 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
Ddac_sam0.c32 const struct pinctrl_dev_config *pcfg; member
96 retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in dac_sam0_init()
133 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
/Zephyr-latest/drivers/mdio/
Dmdio_esp32.c30 const struct pinctrl_dev_config *pcfg; member
97 res = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in mdio_esp32_initialize()
132 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
/Zephyr-latest/soc/nordic/nrf54h/gpd/include/nrf/
Dgpd.h43 int nrf_gpd_retain_pins_set(const struct pinctrl_dev_config *pcfg, bool retain);

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