| /Zephyr-Core-3.7.0/scripts/kconfig/ |
| D | hardened.csv | 1 BOOT_BANNER,n
4 BT_CONN_DISABLE_SECURITY,n
5 BT_KEYS_LOG_LEVEL_DBG,n
6 BT_SMP_LOG_LEVEL_DBG,n
7 BT_FIXED_PASSKEY,n
8 BT_LOG_SNIFFER_INFO,n
9 BT_OOB_DATA_FIXED,n
11 BT_STORE_DEBUG_KEYS,n
12 BT_TESTING,n
13 BT_USE_DEBUG_KEYS,n
[all …]
|
| /Zephyr-Core-3.7.0/soc/nuvoton/npcx/npcx7/ |
| D | soc.h | 13 #define NPCX_DEVALT_OFFSET(n) (0x010 + n) argument
14 #define NPCX_PUPD_EN_OFFSET(n) (0x028 + n) argument
15 #define NPCX_LV_GPIO_CTL_OFFSET(n) ((n < 5) ? (0x02a + n) : (0x021 + n)) argument
16 #define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n) argument
19 #define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 2) + ((n < 5) ? 0 : 0x01e)) argument
20 #define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 2) + ((n < 5) ? 0 : 0x01e)) argument
21 #define NPCX_WKMOD_OFFSET(n) (0x070 + n) argument
22 #define NPCX_WKPND_OFFSET(n) (0x00a + (n * 4) + ((n < 5) ? 0 : 0x010)) argument
23 #define NPCX_WKPCL_OFFSET(n) (0x00c + (n * 4) + ((n < 5) ? 0 : 0x010)) argument
24 #define NPCX_WKEN_OFFSET(n) (0x01e + (n * 2) + ((n < 5) ? 0 : 0x012)) argument
[all …]
|
| /Zephyr-Core-3.7.0/soc/nuvoton/npcx/npcx9/ |
| D | soc.h | 13 #define NPCX_DEVALT_OFFSET(n) (0x010 + n) argument
14 #define NPCX_PUPD_EN_OFFSET(n) (0x028 + n) argument
15 #define NPCX_LV_GPIO_CTL_OFFSET(n) ((n < 5) ? (0x02a + n) : (0x021 + n)) argument
16 #define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n) argument
19 #define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 0x010)) argument
20 #define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 0x010)) argument
21 #define NPCX_WKMOD_OFFSET(n) (0x002 + (n * 0x010)) argument
22 #define NPCX_WKPND_OFFSET(n) (0x003 + (n * 0x010)) argument
23 #define NPCX_WKPCL_OFFSET(n) (0x004 + (n * 0x010)) argument
24 #define NPCX_WKEN_OFFSET(n) (0x005 + (n * 0x010)) argument
[all …]
|
| /Zephyr-Core-3.7.0/include/zephyr/math/ |
| D | ilog2.h | 39 #define ilog2_compile_time_const_u32(n) \ argument
41 ((n) < 2) ? 0 : \
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
49 (((n) & BIT(24)) == BIT(24)) ? 24 : \
[all …]
|
| /Zephyr-Core-3.7.0/samples/net/cloud/mqtt_azure/src/ |
| D | digicert.cer | 2 "-----BEGIN CERTIFICATE-----\r\n"
3 "MIIDdzCCAl+gAwIBAgIEAgAAuTANBgkqhkiG9w0BAQUFADBaMQswCQYDVQQGEwJJ\r\n"
4 "RTESMBAGA1UEChMJQmFsdGltb3JlMRMwEQYDVQQLEwpDeWJlclRydXN0MSIwIAYD\r\n"
5 "VQQDExlCYWx0aW1vcmUgQ3liZXJUcnVzdCBSb290MB4XDTAwMDUxMjE4NDYwMFoX\r\n"
6 "DTI1MDUxMjIzNTkwMFowWjELMAkGA1UEBhMCSUUxEjAQBgNVBAoTCUJhbHRpbW9y\r\n"
7 "ZTETMBEGA1UECxMKQ3liZXJUcnVzdDEiMCAGA1UEAxMZQmFsdGltb3JlIEN5YmVy\r\n"
8 "VHJ1c3QgUm9vdDCCASIwDQYJKoZIhvcNAQEBBQADggEPADCCAQoCggEBAKMEuyKr\r\n"
9 "mD1X6CZymrV51Cni4eiVgLGw41uOKymaZN+hXe2wCQVt2yguzmKiYv60iNoS6zjr\r\n"
10 "IZ3AQSsBUnuId9Mcj8e6uYi1agnnc+gRQKfRzMpijS3ljwumUNKoUMMo6vWrJYeK\r\n"
11 "mpYcqWe4PwzV9/lSEy/CG9VwcPCPwBLKBsua4dnKM3p31vjsufFoREJIE9LAwqSu\r\n"
[all …]
|
| /Zephyr-Core-3.7.0/samples/bluetooth/central_hr/ |
| D | prj_minimal.conf | 6 CONFIG_I2C=n
7 CONFIG_WATCHDOG=n
8 CONFIG_PINCTRL=n
9 CONFIG_SPI=n
10 CONFIG_GPIO=n
11 CONFIG_SERIAL=n
14 CONFIG_PM=n
17 CONFIG_DYNAMIC_INTERRUPTS=n
18 CONFIG_IRQ_OFFLOAD=n
21 CONFIG_THREAD_STACK_INFO=n
[all …]
|
| /Zephyr-Core-3.7.0/samples/bluetooth/peripheral_hr/ |
| D | prj_minimal.conf | 5 CONFIG_BT_DIS_PNP=n
12 CONFIG_I2C=n
13 CONFIG_WATCHDOG=n
14 CONFIG_PINCTRL=n
15 CONFIG_SPI=n
16 CONFIG_GPIO=n
17 CONFIG_SERIAL=n
20 CONFIG_PM=n
23 CONFIG_DYNAMIC_INTERRUPTS=n
24 CONFIG_IRQ_OFFLOAD=n
[all …]
|
| /Zephyr-Core-3.7.0/soc/nuvoton/npcx/npcx4/ |
| D | soc.h | 13 #define NPCX_DEVALT_OFFSET(n) (0x010 + n) argument
14 #define NPCX_PUPD_EN_OFFSET(n) (0x02b + n) argument
15 #define NPCX_LV_GPIO_CTL_OFFSET(n) (0x150 + n) argument
16 #define NPCX_DEVALT_LK_OFFSET(n) (0x210 + n) argument
19 #define NPCX_WKEDG_OFFSET(n) (0x000 + (n * 0x010)) argument
20 #define NPCX_WKAEDG_OFFSET(n) (0x001 + (n * 0x010)) argument
21 #define NPCX_WKMOD_OFFSET(n) (0x002 + (n * 0x010)) argument
22 #define NPCX_WKPND_OFFSET(n) (0x003 + (n * 0x010)) argument
23 #define NPCX_WKPCL_OFFSET(n) (0x004 + (n * 0x010)) argument
24 #define NPCX_WKEN_OFFSET(n) (0x005 + (n * 0x010)) argument
[all …]
|
| /Zephyr-Core-3.7.0/samples/net/sockets/big_http_download/src/ |
| D | isrgrootx1.pem | 1 "-----BEGIN CERTIFICATE-----\n"
2 "MIIFazCCA1OgAwIBAgIRAIIQz7DSQONZRGPgu2OCiwAwDQYJKoZIhvcNAQELBQAw\n"
3 "TzELMAkGA1UEBhMCVVMxKTAnBgNVBAoTIEludGVybmV0IFNlY3VyaXR5IFJlc2Vh\n"
4 "cmNoIEdyb3VwMRUwEwYDVQQDEwxJU1JHIFJvb3QgWDEwHhcNMTUwNjA0MTEwNDM4\n"
5 "WhcNMzUwNjA0MTEwNDM4WjBPMQswCQYDVQQGEwJVUzEpMCcGA1UEChMgSW50ZXJu\n"
6 "ZXQgU2VjdXJpdHkgUmVzZWFyY2ggR3JvdXAxFTATBgNVBAMTDElTUkcgUm9vdCBY\n"
7 "MTCCAiIwDQYJKoZIhvcNAQEBBQADggIPADCCAgoCggIBAK3oJHP0FDfzm54rVygc\n"
8 "h77ct984kIxuPOZXoHj3dcKi/vVqbvYATyjb3miGbESTtrFj/RQSa78f0uoxmyF+\n"
9 "0TM8ukj13Xnfs7j/EvEhmkvBioZxaUpmZmyPfjxwv60pIgbz5MDmgK7iS4+3mX6U\n"
10 "A5/TR5d8mUgjU+g4rk8Kb4Mu0UlXjIB0ttov0DiNewNwIRt18jA8+o+u3dpjq+sW\n"
[all …]
|
| D | DigiCertGlobalRootG2.crt.pem | 1 "-----BEGIN CERTIFICATE-----\n"
2 "MIIDjjCCAnagAwIBAgIQAzrx5qcRqaC7KGSxHQn65TANBgkqhkiG9w0BAQsFADBh\n"
3 "MQswCQYDVQQGEwJVUzEVMBMGA1UEChMMRGlnaUNlcnQgSW5jMRkwFwYDVQQLExB3\n"
4 "d3cuZGlnaWNlcnQuY29tMSAwHgYDVQQDExdEaWdpQ2VydCBHbG9iYWwgUm9vdCBH\n"
5 "MjAeFw0xMzA4MDExMjAwMDBaFw0zODAxMTUxMjAwMDBaMGExCzAJBgNVBAYTAlVT\n"
6 "MRUwEwYDVQQKEwxEaWdpQ2VydCBJbmMxGTAXBgNVBAsTEHd3dy5kaWdpY2VydC5j\n"
7 "b20xIDAeBgNVBAMTF0RpZ2lDZXJ0IEdsb2JhbCBSb290IEcyMIIBIjANBgkqhkiG\n"
8 "9w0BAQEFAAOCAQ8AMIIBCgKCAQEAuzfNNNx7a8myaJCtSnX/RrohCgiN9RlUyfuI\n"
9 "2/Ou8jqJkTx65qsGGmvPrC3oXgkkRLpimn7Wo6h+4FR1IAWsULecYxpsMNzaHxmx\n"
10 "1x7e/dfgy5SDN67sH0NO3Xss0r0upS/kqbitOtSZpLYl6ZtrAGCSYP9PIUkY92eQ\n"
[all …]
|
| /Zephyr-Core-3.7.0/tests/bluetooth/init/ |
| D | prj_ctlr_tiny.conf | 5 CONFIG_BT_CTLR_CONN_PARAM_REQ=n
6 CONFIG_BT_CTLR_EXT_REJ_IND=n
7 CONFIG_BT_CTLR_PER_INIT_FEAT_XCHG=n
8 CONFIG_BT_CTLR_LE_PING=n
9 CONFIG_BT_CTLR_PRIVACY=n
10 CONFIG_BT_CTLR_EXT_SCAN_FP=n
11 CONFIG_BT_DATA_LEN_UPDATE=n
12 CONFIG_BT_PHY_UPDATE=n
13 CONFIG_BT_CTLR_CHAN_SEL_2=n
14 CONFIG_BT_CTLR_MIN_USED_CHAN=n
[all …]
|
| D | prj_ctlr_4_0.conf | 5 CONFIG_BT_CTLR_CONN_PARAM_REQ=n
6 CONFIG_BT_CTLR_LE_PING=n
7 CONFIG_BT_CTLR_PRIVACY=n
8 CONFIG_BT_CTLR_EXT_SCAN_FP=n
9 CONFIG_BT_DATA_LEN_UPDATE=n
10 CONFIG_BT_PHY_UPDATE=n
11 CONFIG_BT_CTLR_CHAN_SEL_2=n
12 CONFIG_BT_CTLR_MIN_USED_CHAN=n
13 CONFIG_BT_CTLR_ADV_EXT=n
20 CONFIG_BT_CTLR_RADIO_ENABLE_FAST=n
[all …]
|
| /Zephyr-Core-3.7.0/samples/basic/minimal/ |
| D | common.conf | 2 CONFIG_I2C=n
3 CONFIG_WATCHDOG=n
4 CONFIG_GPIO=n
5 CONFIG_PINCTRL=n
6 CONFIG_SPI=n
7 CONFIG_SERIAL=n
8 CONFIG_FLASH=n
11 CONFIG_PM=n
14 CONFIG_DYNAMIC_INTERRUPTS=n
15 CONFIG_IRQ_OFFLOAD=n
[all …]
|
| /Zephyr-Core-3.7.0/drivers/sensor/nxp/qdec_nxp_s32/ |
| D | qdec_nxp_s32.c | 207 #define EMIOS_NXP_S32_MCB_OVERFLOW_CALLBACK(n) \ argument
208 static void qdec##n##_emios_overflow_count_cw_callback(void) \
210 qdec_emios_overflow_count_cw_callback(DEVICE_DT_INST_GET(n)); \
213 static void qdec##n##_emios_overflow_count_ccw_callback(void) \
215 qdec_emios_overflow_count_ccw_callback(DEVICE_DT_INST_GET(n)); \
236 #define LogicInputCfg_Common(n, mux_sel_idx) \ argument
238 .MuxSel = DT_INST_PROP_BY_IDX(n, lcu_mux_sel, mux_sel_idx), \
242 #define LogicInput_Config_Common(n, hw_lc_input_id, logic_input_n_cfg) \ argument
245 .HwInstId = LCU_NXP_S32_GET_INSTANCE(DT_INST_PHANDLE(n, lcu)), \
246 .HwLcInputId = DT_INST_PROP_BY_IDX(n, lcu_input_idx, hw_lc_input_id), \
[all …]
|
| /Zephyr-Core-3.7.0/drivers/gpio/ |
| D | gpio_nct38xx.h | 19 #define NCT38XX_REG_GPIO_DATA_IN(n) (0xC0 + ((n) * 8)) argument
20 #define NCT38XX_REG_GPIO_DATA_OUT(n) (0xC1 + ((n) * 8)) argument
21 #define NCT38XX_REG_GPIO_DIR(n) (0xC2 + ((n) * 8)) argument
22 #define NCT38XX_REG_GPIO_OD_SEL(n) (0xC3 + ((n) * 8)) argument
23 #define NCT38XX_REG_GPIO_ALERT_RISE(n) (0xC4 + ((n) * 8)) argument
24 #define NCT38XX_REG_GPIO_ALERT_FALL(n) (0xC5 + ((n) * 8)) argument
25 #define NCT38XX_REG_GPIO_ALERT_LEVEL(n) (0xC6 + ((n) * 8)) argument
26 #define NCT38XX_REG_GPIO_ALERT_MASK(n) (0xC7 + ((n) * 8)) argument
28 #define NCT38XX_REG_GPIO_ALERT_STAT(n) (0xD4 + (n)) argument
|
| /Zephyr-Core-3.7.0/drivers/memc/ |
| D | memc_nxp_s32_qspi.c | 79 #define QSPI_DATA_CFG(n) \ argument
82 DT_INST_STRING_UPPER_TOKEN(n, data_rate)), \
83 .dataAlign = COND_CODE_1(DT_INST_PROP(n, hold_time_2x), \
88 #define QSPI_ADDR_CFG(n) \ argument
90 .columnAddr = DT_INST_PROP_OR(n, column_space, 0), \
91 .wordAddresable = DT_INST_PROP(n, word_addressable), \
94 #define QSPI_BYTES_SWAP_ADDR(n) \ argument
96 (.byteSwap = DT_INST_PROP(n, byte_swapping),))
98 #define QSPI_SAMPLE_DELAY(n) \ argument
99 COND_CODE_1(DT_INST_PROP(n, sample_delay_half_cycle), \
[all …]
|
| /Zephyr-Core-3.7.0/lib/libc/minimal/source/string/ |
| D | string.c | 42 char *strncpy(char *ZRESTRICT d, const char *ZRESTRICT s, size_t n) in strncpy() argument
46 while ((n > 0) && (*s != '\0')) { in strncpy()
50 n--; in strncpy()
53 while (n > 0) { in strncpy()
56 n--; in strncpy()
109 size_t n = 0; in strlen() local
113 n++; in strlen()
116 return n; in strlen()
143 int strncmp(const char *s1, const char *s2, size_t n) in strncmp() argument
145 while ((n > 0) && (*s1 == *s2) && (*s1 != '\0')) { in strncmp()
[all …]
|
| /Zephyr-Core-3.7.0/drivers/mbox/ |
| D | mbox_nxp_s32_mru.c | 188 #define MRU_BASE(n) ((RTU_MRU_Type *)DT_INST_REG_ADDR(n)) argument
189 #define MRU_RX_CHANNELS(n) DT_INST_PROP_OR(n, rx_channels, 0) argument
190 #define MRU_MBOX_ADDR(n, ch, mb) \ argument
191 (DT_INST_REG_ADDR(n) + ((ch + 1) * MRU_CHANNEL_OFFSET) + (MRU_MBOX_SIZE * mb))
193 #define MRU_HW_INSTANCE_CHECK(i, n) \ argument
194 ((DT_INST_REG_ADDR(n) == IP_MRU_##i##_BASE) ? i : 0)
196 #define MRU_HW_INSTANCE(n) \ argument
197 LISTIFY(__DEBRACKET RTU_MRU_INSTANCE_COUNT, MRU_HW_INSTANCE_CHECK, (|), n)
199 #define MRU_INIT_IRQ_FUNC(n) \ argument
200 static void nxp_s32_mru_##n##_init_irq(void) \
[all …]
|
| /Zephyr-Core-3.7.0/drivers/interrupt_controller/ |
| D | intc_gic_common_priv.h | 25 #define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4) argument
26 #define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4) argument
27 #define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4) argument
28 #define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4) argument
29 #define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4) argument
30 #define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n) argument
31 #define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4) argument
32 #define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4) argument
33 #define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4) argument
|
| /Zephyr-Core-3.7.0/drivers/misc/nxp_s32_emios/ |
| D | nxp_s32_emios.c | 46 #define NXP_S32_EMIOS_INSTANCE_CHECK(idx, n) \ argument
47 ((DT_INST_REG_ADDR(n) == IP_EMIOS_##idx##_BASE) ? idx : 0)
49 #define NXP_S32_EMIOS_GET_INSTANCE(n) \ argument
50 LISTIFY(__DEBRACKET eMIOS_INSTANCE_COUNT, NXP_S32_EMIOS_INSTANCE_CHECK, (|), n)
52 #define NXP_S32_EMIOS_GENERATE_GLOBAL_CONFIG(n) \ argument
53 BUILD_ASSERT(IN_RANGE(DT_INST_PROP(n, clock_divider), \
56 const Emios_Ip_GlobalConfigType nxp_s32_emios_##n##_global_config = { \
58 .clkDivVal = DT_INST_PROP(n, clock_divider) - 1U, \
77 #define NXP_S32_EMIOS_GENERATE_MASTER_BUS_CONFIG(n) \ argument
78 DT_FOREACH_CHILD_STATUS_OKAY(DT_INST_CHILD(n, master_bus), \
[all …]
|
| /Zephyr-Core-3.7.0/soc/atmel/sam0/common/ |
| D | atmel_sam0_dt.h | 18 #define MCLK_MASK_DT_INT_REG_ADDR(n) \ argument
19 (DT_REG_ADDR(DT_INST_PHANDLE_BY_NAME(n, clocks, mclk)) + \
20 DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, offset))
25 #define ATMEL_SAM0_DT_INST_DMA_CELL(n, name, cell) \ argument
26 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
27 (DT_INST_DMAS_CELL_BY_NAME(n, name, cell)), \
29 #define ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, name) \ argument
30 ATMEL_SAM0_DT_INST_DMA_CELL(n, name, trigsrc)
31 #define ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, name) \ argument
32 ATMEL_SAM0_DT_INST_DMA_CELL(n, name, channel)
[all …]
|
| /Zephyr-Core-3.7.0/arch/x86/include/intel64/ |
| D | kernel_arch_data.h | 43 #define TRAMPOLINE_STACK(n) \ argument
44 uint8_t z_x86_trampoline_stack##n[Z_X86_TRAMPOLINE_STACK_SIZE] \
47 #define TRAMPOLINE_INIT(n) \ argument
48 .ist2 = (uint64_t)z_x86_trampoline_stack##n + Z_X86_TRAMPOLINE_STACK_SIZE,
50 #define TRAMPOLINE_STACK(n) argument
51 #define TRAMPOLINE_INIT(n) argument
54 #define ACPI_CPU_INIT(n, _) \ argument
55 uint8_t z_x86_exception_stack##n[CONFIG_X86_EXCEPTION_STACK_SIZE] __aligned(16); \
56 uint8_t z_x86_nmi_stack##n[CONFIG_X86_EXCEPTION_STACK_SIZE] __aligned(16); \
57 TRAMPOLINE_STACK(n); \
[all …]
|
| /Zephyr-Core-3.7.0/samples/modules/tflite-micro/hello_world/train/ |
| D | train_hello_world_model.ipynb | 23 "# Train a Simple TensorFlow Lite for Microcontrollers model\n",
24 "\n",
25 …kB model using TensorFlow and converting it for use with TensorFlow Lite for Microcontrollers. \n",
26 "\n",
27 …e) function. This will result in a model that can take a value, `x`, and predict its sine, `y`.\n",
28 "\n",
29 …nsorFlow Lite for MicroControllers](https://www.tensorflow.org/lite/microcontrollers/overview).\n",
30 "\n",
31 "<table class=\"tfo-notebook-buttons\" align=\"left\">\n",
32 " <td>\n",
[all …]
|
| /Zephyr-Core-3.7.0/drivers/ethernet/ |
| D | eth_nxp_s32_netc_vsi.c | 82 #define NETC_VSI_INSTANCE_DEFINE(n) \ argument
83 NETC_GENERATE_MAC_ADDRESS(n) \
85 void nxp_s32_eth_vsi##n##_rx_event(uint8_t chan, const uint32_t *buf, uint8_t buf_size) \
87 Netc_Eth_Ip_MSIX_Rx(NETC_SI_NXP_S32_HW_INSTANCE(n)); \
90 static void nxp_s32_eth##n##_rx_callback(const uint8_t unused, const uint8_t ring) \
92 const struct device *dev = DEVICE_DT_INST_GET(n); \
101 static Netc_Eth_Ip_StateType nxp_s32_eth##n##_state; \
102 Netc_Eth_Ip_VsiToPsiMsgType nxp_s32_eth##n##_vsi2psi_msg \
105 nxp_s32_eth##n##_mac_filter_hash_table[CONFIG_ETH_NXP_S32_MAC_FILTER_TABLE_SIZE]; \
107 NETC_RX_RING(n, TX_RING_IDX, CONFIG_ETH_NXP_S32_RX_RING_LEN, \
[all …]
|
| D | eth_nxp_s32_netc_psi.c | 235 #define NETC_VSI_RX_MSG_BUF(node, prop, idx, n) \ argument
240 _CONCAT3(nxp_s32_eth##n##_vsi, DT_PROP_BY_IDX(node, prop, idx), _rx_msg_buf) \
243 #define NETC_VSI_RX_MSG_BUF_ARRAY(node, prop, idx, n) \ argument
245 &_CONCAT3(nxp_s32_eth##n##_vsi, DT_PROP_BY_IDX(node, prop, idx), _rx_msg_buf)
247 #define NETC_SWITCH_PORT_CFG(_, n) \ argument
249 .ePort = &nxp_s32_eth##n##_switch_port_egress_cfg, \
250 .iPort = &nxp_s32_eth##n##_switch_port_ingress_cfg, \
258 #define PHY_NODE(n) DT_INST_PHANDLE(n, phy_handle) argument
259 #define INIT_VSIS(n) DT_INST_NODE_HAS_PROP(n, vsis) argument
261 #define NETC_PSI_INSTANCE_DEFINE(n) \ argument
[all …]
|
