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Searched refs:mdiv (Results 1 – 4 of 4) sorted by relevance

/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_agilex_ll.c56 uint32_t clk_psrc, mdiv, ref_clk; in get_clk_freq() local
77 mdiv = CLKMGR_PLLM_MDIV(mmio_read_32(pllm_reg)); in get_clk_freq()
78 ref_clk *= mdiv; in get_clk_freq()
Dclock_control_agilex5_ll.c84 uint32_t clk_psrc, mdiv, ref_clk; in get_clk_freq() local
107 mdiv = CLKMGR_PLLM_MDIV(sys_read32(pllm_reg)); in get_clk_freq()
108 ref_clk *= mdiv; in get_clk_freq()
/Zephyr-Core-3.7.0/soc/snps/hsdk/
DCMakeLists.txt7 # -mcpu=hs38_linux includes -matomic -mcode-density -mdiv-rem
/Zephyr-Core-3.7.0/drivers/dai/intel/ssp/
Dssp.c1146 uint32_t mdiv; in dai_ssp_bclk_prepare_enable() local
1159 &mdiv, &need_ecs); in dai_ssp_bclk_prepare_enable()
1173 mdiv = ft[DAI_INTEL_SSP_DEFAULT_IDX].freq / ssp_plat_data->params.bclk_rate; in dai_ssp_bclk_prepare_enable()
1183 mdiv -= 1; in dai_ssp_bclk_prepare_enable()
1186 if (mdiv > (SSCR0_SCR_MASK >> 8)) { in dai_ssp_bclk_prepare_enable()
1187 LOG_ERR("divisor %d is not within SCR range", mdiv); in dai_ssp_bclk_prepare_enable()
1194 sscr0 |= SSCR0_SCR(mdiv); in dai_ssp_bclk_prepare_enable()