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/Zephyr-Core-3.7.0/drivers/fpga/
Dfpga_altera_agilex_bridge.c122 uint32_t mbox_idx = 0; in smc_callback() local
153 for (mbox_idx = 0; mbox_idx < resp_len; mbox_idx++) { in smc_callback()
154 LOG_DBG("\t\t[%4d] %08x", mbox_idx, resp_data[mbox_idx]); in smc_callback()
155 private_data->mbox_response_data[mbox_idx] = resp_data[mbox_idx]; in smc_callback()
228 for (int32_t mbox_idx = 0; mbox_idx < request.a3 / 4; mbox_idx++) { in smc_send() local
229 LOG_DBG("\t [%d ] %08x", mbox_idx, cmd_addr[mbox_idx]); in smc_send()