mainpll_nocdiv (reference) in projects: Zephyr-Core-3.7.0

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/Zephyr-Core-3.7.0/drivers/clock_control/
D	clock_control_agilex5_ll.c	`149 uint32_t mainpll_nocdiv, l4_sp_clk; in get_uart_clk() local 151 mainpll_nocdiv = sys_read32(clock_agilex5_ll.mainpll_addr + CLKMGR_MAINPLL_NOCDIV); in get_uart_clk() 152 mainpll_nocdiv = CLKMGR_MAINPLL_L4SPDIV(mainpll_nocdiv); in get_uart_clk() 154 l4_sp_clk = (get_l3_clk() >> mainpll_nocdiv); in get_uart_clk()`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
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Zephyr-Core-3.5.0
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