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Searched refs:mainpll_addr (Results 1 – 1 of 1) sorted by relevance

/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_control_agilex5_ll.c18 mm_reg_t mainpll_addr; member
33 clock_agilex5_ll.mainpll_addr = clock_agilex5_ll.base_addr + CLKMGR_MAINPLL_OFFSET; in clock_agilex5_ll_init()
87 clk_psrc = sys_read32(clock_agilex5_ll.mainpll_addr + psrc_reg); in get_clk_freq()
91 pllm_reg = clock_agilex5_ll.mainpll_addr + CLKMGR_MAINPLL_PLLM; in get_clk_freq()
92 pllc_reg = clock_agilex5_ll.mainpll_addr + main_pllc; in get_clk_freq()
93 pllglob_reg = clock_agilex5_ll.mainpll_addr + CLKMGR_MAINPLL_PLLGLOB; in get_clk_freq()
151 mainpll_nocdiv = sys_read32(clock_agilex5_ll.mainpll_addr + CLKMGR_MAINPLL_NOCDIV); in get_uart_clk()