Searched refs:icr (Results 1 – 9 of 9) sorted by relevance
| /Zephyr-Core-3.7.0/drivers/gpio/ |
| D | gpio_mcux_igpio.c | 274 uint8_t icr; in mcux_igpio_pin_interrupt_configure() local
288 icr = 3; in mcux_igpio_pin_interrupt_configure()
291 icr = 2; in mcux_igpio_pin_interrupt_configure()
294 icr = 1; in mcux_igpio_pin_interrupt_configure()
296 icr = 0; in mcux_igpio_pin_interrupt_configure()
301 base->ICR1 = (base->ICR1 & ~(3 << shift)) | (icr << shift); in mcux_igpio_pin_interrupt_configure()
304 base->ICR2 = (base->ICR2 & ~(3 << shift)) | (icr << shift); in mcux_igpio_pin_interrupt_configure()
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| D | gpio_mcux.c | 297 uint32_t icr = get_gpio_icr_irqc_value_from_flags(dev, pin, mode, trig); in gpio_mcux_pin_interrupt_configure() local
299 gpio_base->ICR[pin] = (gpio_base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | icr; in gpio_mcux_pin_interrupt_configure()
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| /Zephyr-Core-3.7.0/drivers/timer/ |
| D | apic_tsc.c | 120 uint64_t icr = (delta_cycles * APIC_TIMER_TSC_M) / APIC_TIMER_TSC_N; in set_trigger() local
123 icr = CLAMP(icr, 1, UINT32_MAX); in set_trigger()
124 x86_write_loapic(LOAPIC_TIMER_ICR, icr); in set_trigger()
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| /Zephyr-Core-3.7.0/drivers/ethernet/ |
| D | eth_e1000.c | 176 uint32_t icr = ior32(dev, ICR); /* Cleared upon read */ in e1000_isr() local
178 icr &= ~(ICR_TXDW | ICR_TXQE); in e1000_isr()
180 if (icr & ICR_RXO) { in e1000_isr()
183 icr &= ~ICR_RXO; in e1000_isr()
192 if (icr) { in e1000_isr()
193 LOG_ERR("Unhandled interrupt, ICR: 0x%x", icr); in e1000_isr()
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| /Zephyr-Core-3.7.0/drivers/spi/ |
| D | spi_dw_regs.h | 66 DEFINE_TEST_BIT_OP(icr, DW_SPI_REG_ICR, DW_SPI_SR_ICR_BIT)
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| /Zephyr-Core-3.7.0/drivers/serial/ |
| D | uart_pl011_registers.h | 35 uint32_t icr; member
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| D | uart_lpc11u6x.h | 116 volatile uint32_t icr; /* IrDA Control */ member
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| D | uart_stellaris.c | 53 uint32_t icr; member
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| D | uart_pl011.c | 522 get_uart(dev)->icr = PL011_IMSC_MASK_ALL; in pl011_init()
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