1 /*
2 * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_it8xxx2_i2c
8
9 #include <zephyr/drivers/gpio.h>
10 #include <zephyr/drivers/i2c.h>
11 #include <zephyr/drivers/pinctrl.h>
12 #include <zephyr/irq.h>
13 #include <zephyr/kernel.h>
14 #include <errno.h>
15 #include <ilm.h>
16 #include <soc.h>
17 #include <soc_dt.h>
18 #include <zephyr/dt-bindings/i2c/it8xxx2-i2c.h>
19 #include <zephyr/pm/policy.h>
20 #include <zephyr/sys/util.h>
21
22 #include <zephyr/logging/log.h>
23 LOG_MODULE_REGISTER(i2c_ite_it8xxx2, CONFIG_I2C_LOG_LEVEL);
24
25 #include "i2c-priv.h"
26
27 /* Start smbus session from idle state */
28 #define I2C_MSG_START BIT(5)
29
30 #define I2C_LINE_SCL_HIGH BIT(0)
31 #define I2C_LINE_SDA_HIGH BIT(1)
32 #define I2C_LINE_IDLE (I2C_LINE_SCL_HIGH | I2C_LINE_SDA_HIGH)
33
34 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
35 #define I2C_FIFO_MODE_MAX_SIZE 32
36 #define I2C_FIFO_MODE_TOTAL_LEN 255
37 #define I2C_MSG_BURST_READ_MASK (I2C_MSG_RESTART | I2C_MSG_STOP | I2C_MSG_READ)
38 #endif
39
40 struct i2c_it8xxx2_config {
41 void (*irq_config_func)(void);
42 uint32_t bitrate;
43 uint8_t *base;
44 uint8_t *reg_mstfctrl;
45 uint8_t i2c_irq_base;
46 uint8_t port;
47 uint8_t channel_switch_sel;
48 /* SCL GPIO cells */
49 struct gpio_dt_spec scl_gpios;
50 /* SDA GPIO cells */
51 struct gpio_dt_spec sda_gpios;
52 /* I2C alternate configuration */
53 const struct pinctrl_dev_config *pcfg;
54 uint32_t clock_gate_offset;
55 bool fifo_enable;
56 bool push_pull_recovery;
57 };
58
59 enum i2c_pin_fun {
60 SCL = 0,
61 SDA,
62 };
63
64 enum i2c_ch_status {
65 I2C_CH_NORMAL = 0,
66 I2C_CH_REPEAT_START,
67 I2C_CH_WAIT_READ,
68 I2C_CH_WAIT_NEXT_XFER,
69 };
70
71 struct i2c_it8xxx2_data {
72 enum i2c_ch_status i2ccs;
73 struct i2c_msg *active_msg;
74 struct k_mutex mutex;
75 struct k_sem device_sync_sem;
76 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
77 struct i2c_msg *msgs_list;
78 /* Read or write byte counts. */
79 uint32_t bytecnt;
80 /* Number of messages. */
81 uint8_t num_msgs;
82 uint8_t active_msg_index;
83 #endif
84 /* Index into output data */
85 size_t widx;
86 /* Index into input data */
87 size_t ridx;
88 /* operation freq of i2c */
89 uint32_t bus_freq;
90 /* Error code, if any */
91 uint32_t err;
92 /* address of device */
93 uint16_t addr_16bit;
94 /* Frequency setting */
95 uint8_t freq;
96 /* wait for stop bit interrupt */
97 uint8_t stop;
98 };
99
100 enum i2c_host_status {
101 /* Host busy */
102 HOSTA_HOBY = 0x01,
103 /* Finish Interrupt */
104 HOSTA_FINTR = 0x02,
105 /* Device error */
106 HOSTA_DVER = 0x04,
107 /* Bus error */
108 HOSTA_BSER = 0x08,
109 /* Fail */
110 HOSTA_FAIL = 0x10,
111 /* Not response ACK */
112 HOSTA_NACK = 0x20,
113 /* Time-out error */
114 HOSTA_TMOE = 0x40,
115 /* Byte done status */
116 HOSTA_BDS = 0x80,
117 /* Error bit is set */
118 HOSTA_ANY_ERROR = (HOSTA_DVER | HOSTA_BSER | HOSTA_FAIL |
119 HOSTA_NACK | HOSTA_TMOE),
120 /* W/C for next byte */
121 HOSTA_NEXT_BYTE = HOSTA_BDS,
122 /* W/C host status register */
123 HOSTA_ALL_WC_BIT = (HOSTA_FINTR | HOSTA_ANY_ERROR | HOSTA_BDS),
124 };
125
126 enum i2c_reset_cause {
127 I2C_RC_NO_IDLE_FOR_START = 1,
128 I2C_RC_TIMEOUT,
129 };
130
i2c_parsing_return_value(const struct device * dev)131 static int i2c_parsing_return_value(const struct device *dev)
132 {
133 const struct i2c_it8xxx2_config *config = dev->config;
134 struct i2c_it8xxx2_data *data = dev->data;
135
136 if (!data->err) {
137 return 0;
138 }
139
140 if (data->err == ETIMEDOUT) {
141 /* Connection timed out */
142 LOG_ERR("I2C ch%d Address:0x%X Transaction time out.",
143 config->port, data->addr_16bit);
144 } else {
145 LOG_DBG("I2C ch%d Address:0x%X Host error bits message:",
146 config->port, data->addr_16bit);
147 /* Host error bits message*/
148 if (data->err & HOSTA_TMOE) {
149 LOG_ERR("Time-out error: hardware time-out error.");
150 }
151 if (data->err & HOSTA_NACK) {
152 LOG_DBG("NACK error: device does not response ACK.");
153 }
154 if (data->err & HOSTA_FAIL) {
155 LOG_ERR("Fail: a processing transmission is killed.");
156 }
157 if (data->err & HOSTA_BSER) {
158 LOG_ERR("BUS error: SMBus has lost arbitration.");
159 }
160 }
161
162 return -EIO;
163 }
164
i2c_get_line_levels(const struct device * dev)165 static int i2c_get_line_levels(const struct device *dev)
166 {
167 const struct i2c_it8xxx2_config *config = dev->config;
168 uint8_t *base = config->base;
169
170 return (IT8XXX2_SMB_SMBPCTL(base) &
171 (IT8XXX2_SMB_SMBDCS | IT8XXX2_SMB_SMBCS));
172 }
173
i2c_is_busy(const struct device * dev)174 static int i2c_is_busy(const struct device *dev)
175 {
176 const struct i2c_it8xxx2_config *config = dev->config;
177 uint8_t *base = config->base;
178
179 return (IT8XXX2_SMB_HOSTA(base) &
180 (HOSTA_HOBY | HOSTA_ALL_WC_BIT));
181 }
182
i2c_bus_not_available(const struct device * dev)183 static int i2c_bus_not_available(const struct device *dev)
184 {
185 if (i2c_is_busy(dev) ||
186 (i2c_get_line_levels(dev) != I2C_LINE_IDLE)) {
187 return -EIO;
188 }
189
190 return 0;
191 }
192
i2c_reset(const struct device * dev)193 static void i2c_reset(const struct device *dev)
194 {
195 const struct i2c_it8xxx2_config *config = dev->config;
196 uint8_t *base = config->base;
197
198 /* bit1, kill current transaction. */
199 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_KILL;
200 IT8XXX2_SMB_HOCTL(base) = 0;
201 /* W/C host status register */
202 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
203 }
204
205 /*
206 * Set i2c standard port (A, B, or C) runs at 400kHz by using timing registers
207 * (offset 0h ~ 7h).
208 */
i2c_standard_port_timing_regs_400khz(uint8_t port)209 static void i2c_standard_port_timing_regs_400khz(uint8_t port)
210 {
211 /* Port clock frequency depends on setting of timing registers. */
212 IT8XXX2_SMB_SCLKTS(port) = 0;
213 /* Suggested setting of timing registers of 400kHz. */
214 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
215 IT8XXX2_SMB_4P7USL = 0x16;
216 IT8XXX2_SMB_4P0USL = 0x11;
217 IT8XXX2_SMB_300NS = 0x8;
218 IT8XXX2_SMB_250NS = 0x8;
219 IT8XXX2_SMB_45P3USL = 0xff;
220 IT8XXX2_SMB_45P3USH = 0x3;
221 IT8XXX2_SMB_4P7A4P0H = 0;
222 #else
223 IT8XXX2_SMB_4P7USL = 0x3;
224 IT8XXX2_SMB_4P0USL = 0;
225 IT8XXX2_SMB_300NS = 0x1;
226 IT8XXX2_SMB_250NS = 0x5;
227 IT8XXX2_SMB_45P3USL = 0x6a;
228 IT8XXX2_SMB_45P3USH = 0x1;
229 IT8XXX2_SMB_4P7A4P0H = 0;
230 #endif
231 }
232
233 /* Set clock frequency for i2c port A, B , or C */
i2c_standard_port_set_frequency(const struct device * dev,int freq_hz,int freq_set)234 static void i2c_standard_port_set_frequency(const struct device *dev,
235 int freq_hz, int freq_set)
236 {
237 const struct i2c_it8xxx2_config *config = dev->config;
238
239 /*
240 * If port's clock frequency is 400kHz, we use timing registers
241 * for setting. So we can adjust tlow to meet timing.
242 * The others use basic 50/100/1000 KHz setting.
243 */
244 if (freq_hz == I2C_BITRATE_FAST) {
245 i2c_standard_port_timing_regs_400khz(config->port);
246 } else {
247 IT8XXX2_SMB_SCLKTS(config->port) = freq_set;
248 }
249
250 /* This field defines the SMCLK0/1/2 clock/data low timeout. */
251 IT8XXX2_SMB_25MS = I2C_CLK_LOW_TIMEOUT;
252 }
253
i2c_it8xxx2_configure(const struct device * dev,uint32_t dev_config_raw)254 static int i2c_it8xxx2_configure(const struct device *dev,
255 uint32_t dev_config_raw)
256 {
257 const struct i2c_it8xxx2_config *config = dev->config;
258 struct i2c_it8xxx2_data *const data = dev->data;
259 uint32_t freq_set;
260
261 if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
262 return -EINVAL;
263 }
264
265 if (I2C_ADDR_10_BITS & dev_config_raw) {
266 return -EINVAL;
267 }
268
269 data->bus_freq = I2C_SPEED_GET(dev_config_raw);
270
271 switch (data->bus_freq) {
272 case I2C_SPEED_DT:
273 freq_set = IT8XXX2_SMB_SMCLKS_50K;
274 break;
275 case I2C_SPEED_STANDARD:
276 freq_set = IT8XXX2_SMB_SMCLKS_100K;
277 break;
278 case I2C_SPEED_FAST:
279 freq_set = IT8XXX2_SMB_SMCLKS_400K;
280 break;
281 case I2C_SPEED_FAST_PLUS:
282 freq_set = IT8XXX2_SMB_SMCLKS_1M;
283 break;
284 default:
285 return -EINVAL;
286 }
287
288 i2c_standard_port_set_frequency(dev, config->bitrate, freq_set);
289
290 return 0;
291 }
292
i2c_it8xxx2_get_config(const struct device * dev,uint32_t * dev_config)293 static int i2c_it8xxx2_get_config(const struct device *dev,
294 uint32_t *dev_config)
295 {
296 struct i2c_it8xxx2_data *const data = dev->data;
297 uint32_t speed;
298
299 if (!data->bus_freq) {
300 LOG_ERR("The bus frequency is not initially configured.");
301 return -EIO;
302 }
303
304 switch (data->bus_freq) {
305 case I2C_SPEED_DT:
306 case I2C_SPEED_STANDARD:
307 case I2C_SPEED_FAST:
308 case I2C_SPEED_FAST_PLUS:
309 speed = I2C_SPEED_SET(data->bus_freq);
310 break;
311 default:
312 return -ERANGE;
313 }
314
315 *dev_config = (I2C_MODE_CONTROLLER | speed);
316
317 return 0;
318 }
319
i2c_r_last_byte(const struct device * dev)320 void __soc_ram_code i2c_r_last_byte(const struct device *dev)
321 {
322 struct i2c_it8xxx2_data *data = dev->data;
323 const struct i2c_it8xxx2_config *config = dev->config;
324 uint8_t *base = config->base;
325
326 /*
327 * bit5, The firmware shall write 1 to this bit
328 * when the next byte will be the last byte for i2c read.
329 */
330 if ((data->active_msg->flags & I2C_MSG_STOP) &&
331 (data->ridx == data->active_msg->len - 1)) {
332 IT8XXX2_SMB_HOCTL(base) |= IT8XXX2_SMB_LABY;
333 }
334 }
335
i2c_w2r_change_direction(const struct device * dev)336 void __soc_ram_code i2c_w2r_change_direction(const struct device *dev)
337 {
338 const struct i2c_it8xxx2_config *config = dev->config;
339 uint8_t *base = config->base;
340
341 /* I2C switch direction */
342 if (IT8XXX2_SMB_HOCTL2(base) & IT8XXX2_SMB_I2C_SW_EN) {
343 i2c_r_last_byte(dev);
344 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
345 } else {
346 /*
347 * bit2, I2C switch direction wait.
348 * bit3, I2C switch direction enable.
349 */
350 IT8XXX2_SMB_HOCTL2(base) |= IT8XXX2_SMB_I2C_SW_EN |
351 IT8XXX2_SMB_I2C_SW_WAIT;
352 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
353 i2c_r_last_byte(dev);
354 IT8XXX2_SMB_HOCTL2(base) &= ~IT8XXX2_SMB_I2C_SW_WAIT;
355 }
356 }
357
358 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
i2c_fifo_en_w2r(const struct device * dev,bool enable)359 void __soc_ram_code i2c_fifo_en_w2r(const struct device *dev, bool enable)
360 {
361 const struct i2c_it8xxx2_config *config = dev->config;
362 unsigned int key = irq_lock();
363
364 if (enable) {
365 if (config->port == SMB_CHANNEL_A) {
366 IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MAIF |
367 IT8XXX2_SMB_MAIFI;
368 } else if (config->port == SMB_CHANNEL_B) {
369 IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MBCIF |
370 IT8XXX2_SMB_MBIFI;
371 } else if (config->port == SMB_CHANNEL_C) {
372 IT8XXX2_SMB_I2CW2RF |= IT8XXX2_SMB_MBCIF |
373 IT8XXX2_SMB_MCIFI;
374 }
375 } else {
376 if (config->port == SMB_CHANNEL_A) {
377 IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MAIF |
378 IT8XXX2_SMB_MAIFI);
379 } else if (config->port == SMB_CHANNEL_B) {
380 IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MBCIF |
381 IT8XXX2_SMB_MBIFI);
382 } else if (config->port == SMB_CHANNEL_C) {
383 IT8XXX2_SMB_I2CW2RF &= ~(IT8XXX2_SMB_MBCIF |
384 IT8XXX2_SMB_MCIFI);
385 }
386 }
387
388 irq_unlock(key);
389 }
390
i2c_tran_fifo_write_start(const struct device * dev)391 void __soc_ram_code i2c_tran_fifo_write_start(const struct device *dev)
392 {
393 struct i2c_it8xxx2_data *data = dev->data;
394 const struct i2c_it8xxx2_config *config = dev->config;
395 uint32_t i;
396 uint8_t *base = config->base;
397 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
398
399 /* Clear start flag. */
400 data->active_msg->flags &= ~I2C_MSG_START;
401 /* Enable SMB channel in FIFO mode. */
402 *reg_mstfctrl |= IT8XXX2_SMB_FFEN;
403 /* I2C enable. */
404 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
405 IT8XXX2_SMB_I2C_EN |
406 IT8XXX2_SMB_SMHEN;
407 /* Set write byte counts. */
408 IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
409 /*
410 * bit[7:1]: Address of the target.
411 * bit[0]: Direction of the host transfer.
412 */
413 IT8XXX2_SMB_TRASLA(base) = (uint8_t)data->addr_16bit << 1;
414 /* The maximum fifo size is 32 bytes. */
415 data->bytecnt = MIN(data->active_msg->len, I2C_FIFO_MODE_MAX_SIZE);
416
417 for (i = 0; i < data->bytecnt; i++) {
418 /* Set host block data byte. */
419 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
420 }
421 /* Calculate the remaining byte counts. */
422 data->bytecnt = data->active_msg->len - data->bytecnt;
423 /*
424 * bit[6] = 1b: Start.
425 * bit[4:2] = 111b: Extend command.
426 * bit[0] = 1b: Host interrupt enable.
427 */
428 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
429 IT8XXX2_SMB_SMCD_EXTND |
430 IT8XXX2_SMB_INTREN;
431 }
432
i2c_tran_fifo_write_next_block(const struct device * dev)433 void __soc_ram_code i2c_tran_fifo_write_next_block(const struct device *dev)
434 {
435 struct i2c_it8xxx2_data *data = dev->data;
436 const struct i2c_it8xxx2_config *config = dev->config;
437 uint32_t i, _bytecnt;
438 uint8_t *base = config->base;
439 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
440
441 /* The maximum fifo size is 32 bytes. */
442 _bytecnt = MIN(data->bytecnt, I2C_FIFO_MODE_MAX_SIZE);
443
444 for (i = 0; i < _bytecnt; i++) {
445 /* Set host block data byte. */
446 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
447 }
448 /* Clear FIFO block done status. */
449 *reg_mstfctrl |= IT8XXX2_SMB_BLKDS;
450 /* Calculate the remaining byte counts. */
451 data->bytecnt -= _bytecnt;
452 }
453
i2c_tran_fifo_write_finish(const struct device * dev)454 void __soc_ram_code i2c_tran_fifo_write_finish(const struct device *dev)
455 {
456 const struct i2c_it8xxx2_config *config = dev->config;
457 uint8_t *base = config->base;
458
459 /* Clear byte count register. */
460 IT8XXX2_SMB_D0REG(base) = 0;
461 /* W/C */
462 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
463 /* Disable the SMBus host interface. */
464 IT8XXX2_SMB_HOCTL2(base) = 0x00;
465 }
466
i2c_tran_fifo_w2r_change_direction(const struct device * dev)467 int __soc_ram_code i2c_tran_fifo_w2r_change_direction(const struct device *dev)
468 {
469 struct i2c_it8xxx2_data *data = dev->data;
470 const struct i2c_it8xxx2_config *config = dev->config;
471 uint8_t *base = config->base;
472
473 if (++data->active_msg_index >= data->num_msgs) {
474 LOG_ERR("Current message index is error.");
475 data->err = EINVAL;
476 /* W/C */
477 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
478 /* Disable the SMBus host interface. */
479 IT8XXX2_SMB_HOCTL2(base) = 0x00;
480
481 return 0;
482 }
483 /* Set I2C_SW_EN = 1 */
484 IT8XXX2_SMB_HOCTL2(base) |= IT8XXX2_SMB_I2C_SW_EN |
485 IT8XXX2_SMB_I2C_SW_WAIT;
486 IT8XXX2_SMB_HOCTL2(base) &= ~IT8XXX2_SMB_I2C_SW_WAIT;
487 /* Point to the next msg for the read location. */
488 data->active_msg = &data->msgs_list[data->active_msg_index];
489 /* Set read byte counts. */
490 IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
491 data->bytecnt = data->active_msg->len;
492 /* W/C I2C W2R FIFO interrupt status. */
493 IT8XXX2_SMB_IWRFISTA = BIT(config->port);
494
495 return 1;
496 }
497
i2c_tran_fifo_read_start(const struct device * dev)498 void __soc_ram_code i2c_tran_fifo_read_start(const struct device *dev)
499 {
500 struct i2c_it8xxx2_data *data = dev->data;
501 const struct i2c_it8xxx2_config *config = dev->config;
502 uint8_t *base = config->base;
503 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
504
505 /* Clear start flag. */
506 data->active_msg->flags &= ~I2C_MSG_START;
507 /* Enable SMB channel in FIFO mode. */
508 *reg_mstfctrl |= IT8XXX2_SMB_FFEN;
509 /* I2C enable. */
510 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
511 IT8XXX2_SMB_I2C_EN |
512 IT8XXX2_SMB_SMHEN;
513 /* Set read byte counts. */
514 IT8XXX2_SMB_D0REG(base) = data->active_msg->len;
515 /*
516 * bit[7:1]: Address of the target.
517 * bit[0]: Direction of the host transfer.
518 */
519 IT8XXX2_SMB_TRASLA(base) = (uint8_t)(data->addr_16bit << 1) |
520 IT8XXX2_SMB_DIR;
521
522 data->bytecnt = data->active_msg->len;
523 /*
524 * bit[6] = 1b: Start.
525 * bit[4:2] = 111b: Extend command.
526 * bit[0] = 1b: Host interrupt enable.
527 */
528 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
529 IT8XXX2_SMB_SMCD_EXTND |
530 IT8XXX2_SMB_INTREN;
531 }
532
i2c_tran_fifo_read_next_block(const struct device * dev)533 void __soc_ram_code i2c_tran_fifo_read_next_block(const struct device *dev)
534 {
535 struct i2c_it8xxx2_data *data = dev->data;
536 const struct i2c_it8xxx2_config *config = dev->config;
537 uint32_t i;
538 uint8_t *base = config->base;
539 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
540
541 for (i = 0; i < I2C_FIFO_MODE_MAX_SIZE; i++) {
542 /* To get received data. */
543 *(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
544 }
545 /* Clear FIFO block done status. */
546 *reg_mstfctrl |= IT8XXX2_SMB_BLKDS;
547 /* Calculate the remaining byte counts. */
548 data->bytecnt -= I2C_FIFO_MODE_MAX_SIZE;
549 }
550
i2c_tran_fifo_read_finish(const struct device * dev)551 void __soc_ram_code i2c_tran_fifo_read_finish(const struct device *dev)
552 {
553 struct i2c_it8xxx2_data *data = dev->data;
554 const struct i2c_it8xxx2_config *config = dev->config;
555 uint32_t i;
556 uint8_t *base = config->base;
557
558 for (i = 0; i < data->bytecnt; i++) {
559 /* To get received data. */
560 *(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
561 }
562 /* Clear byte count register. */
563 IT8XXX2_SMB_D0REG(base) = 0;
564 /* W/C */
565 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
566 /* Disable the SMBus host interface. */
567 IT8XXX2_SMB_HOCTL2(base) = 0x00;
568
569 }
570
i2c_tran_fifo_write_to_read(const struct device * dev)571 int __soc_ram_code i2c_tran_fifo_write_to_read(const struct device *dev)
572 {
573 struct i2c_it8xxx2_data *data = dev->data;
574 const struct i2c_it8xxx2_config *config = dev->config;
575 uint8_t *base = config->base;
576 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
577 int ret = 1;
578
579 if (data->active_msg->flags & I2C_MSG_START) {
580 /* Enable I2C write to read FIFO mode. */
581 i2c_fifo_en_w2r(dev, 1);
582 i2c_tran_fifo_write_start(dev);
583 } else {
584 /* Check block done status. */
585 if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
586 if (IT8XXX2_SMB_HOCTL2(base) & IT8XXX2_SMB_I2C_SW_EN) {
587 i2c_tran_fifo_read_next_block(dev);
588 } else {
589 i2c_tran_fifo_write_next_block(dev);
590 }
591 } else if (IT8XXX2_SMB_IWRFISTA & BIT(config->port)) {
592 /*
593 * This function returns 0 on a failure to indicate
594 * that the current transaction is completed and
595 * returned the data->err.
596 */
597 ret = i2c_tran_fifo_w2r_change_direction(dev);
598 } else {
599 /* Wait finish. */
600 if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
601 i2c_tran_fifo_read_finish(dev);
602 /* Done doing work. */
603 ret = 0;
604 }
605 }
606 }
607
608 return ret;
609 }
610
i2c_tran_fifo_read(const struct device * dev)611 int __soc_ram_code i2c_tran_fifo_read(const struct device *dev)
612 {
613 struct i2c_it8xxx2_data *data = dev->data;
614 const struct i2c_it8xxx2_config *config = dev->config;
615 uint8_t *base = config->base;
616 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
617
618 if (data->active_msg->flags & I2C_MSG_START) {
619 i2c_tran_fifo_read_start(dev);
620 } else {
621 /* Check block done status. */
622 if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
623 i2c_tran_fifo_read_next_block(dev);
624 } else {
625 /* Wait finish. */
626 if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
627 i2c_tran_fifo_read_finish(dev);
628 /* Done doing work. */
629 return 0;
630 }
631 }
632 }
633
634 return 1;
635 }
636
i2c_tran_fifo_write(const struct device * dev)637 int __soc_ram_code i2c_tran_fifo_write(const struct device *dev)
638 {
639 struct i2c_it8xxx2_data *data = dev->data;
640 const struct i2c_it8xxx2_config *config = dev->config;
641 uint8_t *base = config->base;
642 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
643
644 if (data->active_msg->flags & I2C_MSG_START) {
645 i2c_tran_fifo_write_start(dev);
646 } else {
647 /* Check block done status. */
648 if (*reg_mstfctrl & IT8XXX2_SMB_BLKDS) {
649 i2c_tran_fifo_write_next_block(dev);
650 } else {
651 /* Wait finish. */
652 if ((IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
653 i2c_tran_fifo_write_finish(dev);
654 /* Done doing work. */
655 return 0;
656 }
657 }
658 }
659
660 return 1;
661 }
662
i2c_fifo_transaction(const struct device * dev)663 int __soc_ram_code i2c_fifo_transaction(const struct device *dev)
664 {
665 struct i2c_it8xxx2_data *data = dev->data;
666 const struct i2c_it8xxx2_config *config = dev->config;
667 uint8_t *base = config->base;
668
669 /* Any error. */
670 if (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR) {
671 data->err = (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR);
672 } else {
673 if (data->num_msgs == 2) {
674 return i2c_tran_fifo_write_to_read(dev);
675 } else if (data->active_msg->flags & I2C_MSG_READ) {
676 return i2c_tran_fifo_read(dev);
677 } else {
678 return i2c_tran_fifo_write(dev);
679 }
680 }
681 /* W/C */
682 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
683 /* Disable the SMBus host interface. */
684 IT8XXX2_SMB_HOCTL2(base) = 0x00;
685
686 return 0;
687 }
688
fifo_mode_allowed(const struct device * dev,struct i2c_msg * msgs)689 bool __soc_ram_code fifo_mode_allowed(const struct device *dev,
690 struct i2c_msg *msgs)
691 {
692 struct i2c_it8xxx2_data *data = dev->data;
693 const struct i2c_it8xxx2_config *config = dev->config;
694
695 /*
696 * If the transaction of write or read is divided into two
697 * transfers(not two messages), the FIFO mode does not support.
698 */
699 if (data->i2ccs != I2C_CH_NORMAL) {
700 return false;
701 }
702 /*
703 * FIFO2 only supports one channel of B or C. If the FIFO of
704 * channel is not enabled, it will select PIO mode.
705 */
706 if (!config->fifo_enable) {
707 return false;
708 }
709 /*
710 * When there is only one message, use the FIFO mode transfer
711 * directly.
712 * Transfer payload too long (>255 bytes), use PIO mode.
713 * Write or read of I2C target address without data, used by
714 * cmd_i2c_scan. Use PIO mode.
715 */
716 if (data->num_msgs == 1 && (msgs[0].flags & I2C_MSG_STOP) &&
717 (msgs[0].len <= I2C_FIFO_MODE_TOTAL_LEN) && (msgs[0].len != 0)) {
718 return true;
719 }
720 /*
721 * When there are two messages, we need to judge whether or not there
722 * is I2C_MSG_RESTART flag from the second message, and then decide to
723 * do the FIFO mode or PIO mode transfer.
724 */
725 if (data->num_msgs == 2) {
726 /*
727 * The first of two messages must be write.
728 * Transfer payload too long (>255 bytes), use PIO mode.
729 */
730 if (((msgs[0].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) &&
731 (msgs[0].len <= I2C_FIFO_MODE_TOTAL_LEN)) {
732 /*
733 * The transfer is i2c_burst_read().
734 *
735 * e.g. msg[0].flags = I2C_MSG_WRITE;
736 * msg[1].flags = I2C_MSG_RESTART | I2C_MSG_READ |
737 * I2C_MSG_STOP;
738 */
739 if ((msgs[1].flags == I2C_MSG_BURST_READ_MASK) &&
740 (msgs[1].len <= I2C_FIFO_MODE_TOTAL_LEN)) {
741 return true;
742 }
743 }
744 }
745
746 return false;
747 }
748 #endif
749
i2c_tran_read(const struct device * dev)750 int __soc_ram_code i2c_tran_read(const struct device *dev)
751 {
752 struct i2c_it8xxx2_data *data = dev->data;
753 const struct i2c_it8xxx2_config *config = dev->config;
754 uint8_t *base = config->base;
755
756 if (data->active_msg->flags & I2C_MSG_START) {
757 /* i2c enable */
758 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
759 IT8XXX2_SMB_I2C_EN |
760 IT8XXX2_SMB_SMHEN;
761 /*
762 * bit0, Direction of the host transfer.
763 * bit[1:7}, Address of the targeted slave.
764 */
765 IT8XXX2_SMB_TRASLA(base) = (uint8_t)(data->addr_16bit << 1) |
766 IT8XXX2_SMB_DIR;
767 /* clear start flag */
768 data->active_msg->flags &= ~I2C_MSG_START;
769 /*
770 * bit0, Host interrupt enable.
771 * bit[2:4}, Extend command.
772 * bit5, The firmware shall write 1 to this bit
773 * when the next byte will be the last byte.
774 * bit6, start.
775 */
776 if ((data->active_msg->len == 1) &&
777 (data->active_msg->flags & I2C_MSG_STOP)) {
778 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
779 IT8XXX2_SMB_LABY |
780 IT8XXX2_SMB_SMCD_EXTND |
781 IT8XXX2_SMB_INTREN;
782 } else {
783 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
784 IT8XXX2_SMB_SMCD_EXTND |
785 IT8XXX2_SMB_INTREN;
786 }
787 } else {
788 if ((data->i2ccs == I2C_CH_REPEAT_START) ||
789 (data->i2ccs == I2C_CH_WAIT_READ)) {
790 if (data->i2ccs == I2C_CH_REPEAT_START) {
791 /* write to read */
792 i2c_w2r_change_direction(dev);
793 } else {
794 /* For last byte */
795 i2c_r_last_byte(dev);
796 /* W/C for next byte */
797 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
798 }
799 data->i2ccs = I2C_CH_NORMAL;
800 } else if (IT8XXX2_SMB_HOSTA(base) & HOSTA_BDS) {
801 if (data->ridx < data->active_msg->len) {
802 /* To get received data. */
803 *(data->active_msg->buf++) = IT8XXX2_SMB_HOBDB(base);
804 data->ridx++;
805 /* For last byte */
806 i2c_r_last_byte(dev);
807 /* done */
808 if (data->ridx == data->active_msg->len) {
809 data->active_msg->len = 0;
810 if (data->active_msg->flags & I2C_MSG_STOP) {
811 /* W/C for finish */
812 IT8XXX2_SMB_HOSTA(base) =
813 HOSTA_NEXT_BYTE;
814
815 data->stop = 1;
816 } else {
817 data->i2ccs = I2C_CH_WAIT_READ;
818 return 0;
819 }
820 } else {
821 /* W/C for next byte */
822 IT8XXX2_SMB_HOSTA(base) =
823 HOSTA_NEXT_BYTE;
824 }
825 }
826 }
827 }
828 return 1;
829
830 }
831
i2c_tran_write(const struct device * dev)832 int __soc_ram_code i2c_tran_write(const struct device *dev)
833 {
834 struct i2c_it8xxx2_data *data = dev->data;
835 const struct i2c_it8xxx2_config *config = dev->config;
836 uint8_t *base = config->base;
837
838 if (data->active_msg->flags & I2C_MSG_START) {
839 /* i2c enable */
840 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
841 IT8XXX2_SMB_I2C_EN |
842 IT8XXX2_SMB_SMHEN;
843 /*
844 * bit0, Direction of the host transfer.
845 * bit[1:7}, Address of the targeted slave.
846 */
847 IT8XXX2_SMB_TRASLA(base) = (uint8_t)data->addr_16bit << 1;
848 /* Send first byte */
849 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
850
851 data->widx++;
852 /* clear start flag */
853 data->active_msg->flags &= ~I2C_MSG_START;
854 /*
855 * bit0, Host interrupt enable.
856 * bit[2:4}, Extend command.
857 * bit6, start.
858 */
859 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SRT |
860 IT8XXX2_SMB_SMCD_EXTND |
861 IT8XXX2_SMB_INTREN;
862 } else {
863 /* Host has completed the transmission of a byte */
864 if (IT8XXX2_SMB_HOSTA(base) & HOSTA_BDS) {
865 if (data->widx < data->active_msg->len) {
866 /* Send next byte */
867 IT8XXX2_SMB_HOBDB(base) = *(data->active_msg->buf++);
868
869 data->widx++;
870 /* W/C byte done for next byte */
871 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
872
873 if (data->i2ccs == I2C_CH_REPEAT_START) {
874 data->i2ccs = I2C_CH_NORMAL;
875 }
876 } else {
877 /* done */
878 data->active_msg->len = 0;
879 if (data->active_msg->flags & I2C_MSG_STOP) {
880 /* set I2C_EN = 0 */
881 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN |
882 IT8XXX2_SMB_SMHEN;
883 /* W/C byte done for finish */
884 IT8XXX2_SMB_HOSTA(base) = HOSTA_NEXT_BYTE;
885
886 data->stop = 1;
887 } else {
888 data->i2ccs = I2C_CH_REPEAT_START;
889 return 0;
890 }
891 }
892 }
893 }
894 return 1;
895
896 }
897
i2c_pio_transaction(const struct device * dev)898 int __soc_ram_code i2c_pio_transaction(const struct device *dev)
899 {
900 struct i2c_it8xxx2_data *data = dev->data;
901 const struct i2c_it8xxx2_config *config = dev->config;
902 uint8_t *base = config->base;
903
904 /* any error */
905 if (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR) {
906 data->err = (IT8XXX2_SMB_HOSTA(base) & HOSTA_ANY_ERROR);
907 } else {
908 if (!data->stop) {
909 /*
910 * The return value indicates if there is more data
911 * to be read or written. If the return value = 1,
912 * it means that the interrupt cannot be disable and
913 * continue to transmit data.
914 */
915 if (data->active_msg->flags & I2C_MSG_READ) {
916 return i2c_tran_read(dev);
917 } else {
918 return i2c_tran_write(dev);
919 }
920 }
921 /* wait finish */
922 if (!(IT8XXX2_SMB_HOSTA(base) & HOSTA_FINTR)) {
923 return 1;
924 }
925 }
926 /* W/C */
927 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
928 /* disable the SMBus host interface */
929 IT8XXX2_SMB_HOCTL2(base) = 0x00;
930
931 data->stop = 0;
932 /* done doing work */
933 return 0;
934 }
935
i2c_it8xxx2_transfer(const struct device * dev,struct i2c_msg * msgs,uint8_t num_msgs,uint16_t addr)936 static int i2c_it8xxx2_transfer(const struct device *dev, struct i2c_msg *msgs,
937 uint8_t num_msgs, uint16_t addr)
938 {
939 struct i2c_it8xxx2_data *data = dev->data;
940 const struct i2c_it8xxx2_config *config = dev->config;
941 int res, ret;
942
943 /* Lock mutex of i2c controller */
944 k_mutex_lock(&data->mutex, K_FOREVER);
945 /*
946 * If the transaction of write to read is divided into two
947 * transfers, the repeat start transfer uses this flag to
948 * exclude checking bus busy.
949 */
950 if (data->i2ccs == I2C_CH_NORMAL) {
951 struct i2c_msg *start_msg = &msgs[0];
952
953 /* Make sure we're in a good state to start */
954 if (i2c_bus_not_available(dev)) {
955 /* Recovery I2C bus */
956 i2c_recover_bus(dev);
957 /*
958 * After resetting I2C bus, if I2C bus is not available
959 * (No external pull-up), drop the transaction.
960 */
961 if (i2c_bus_not_available(dev)) {
962 /* Unlock mutex of i2c controller */
963 k_mutex_unlock(&data->mutex);
964 return -EIO;
965 }
966 }
967
968 start_msg->flags |= I2C_MSG_START;
969 }
970 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
971 /* Store num_msgs to data struct. */
972 data->num_msgs = num_msgs;
973 /* Store msgs to data struct. */
974 data->msgs_list = msgs;
975 bool fifo_mode_enable = fifo_mode_allowed(dev, msgs);
976
977 if (fifo_mode_enable) {
978 /* Block to enter power policy. */
979 pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
980 }
981 #endif
982 for (int i = 0; i < num_msgs; i++) {
983
984 data->widx = 0;
985 data->ridx = 0;
986 data->err = 0;
987 data->active_msg = &msgs[i];
988 data->addr_16bit = addr;
989
990 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
991 data->active_msg_index = 0;
992 /*
993 * Start transaction.
994 * The return value indicates if the initial configuration
995 * of I2C transaction for read or write has been completed.
996 */
997 if (fifo_mode_enable) {
998 if (i2c_fifo_transaction(dev)) {
999 /* Enable i2c interrupt */
1000 irq_enable(config->i2c_irq_base);
1001 }
1002 } else
1003 #endif
1004 {
1005 if (i2c_pio_transaction(dev)) {
1006 /* Enable i2c interrupt */
1007 irq_enable(config->i2c_irq_base);
1008 }
1009 }
1010 /* Wait for the transfer to complete */
1011 /* TODO: the timeout should be adjustable */
1012 res = k_sem_take(&data->device_sync_sem, K_MSEC(100));
1013 /*
1014 * The irq will be enabled at the condition of start or
1015 * repeat start of I2C. If timeout occurs without being
1016 * wake up during suspend(ex: interrupt is not fired),
1017 * the irq should be disabled immediately.
1018 */
1019 irq_disable(config->i2c_irq_base);
1020 /*
1021 * The transaction is dropped on any error(timeout, NACK, fail,
1022 * bus error, device error).
1023 */
1024 if (data->err) {
1025 break;
1026 }
1027
1028 if (res != 0) {
1029 data->err = ETIMEDOUT;
1030 /* reset i2c port */
1031 i2c_reset(dev);
1032 LOG_ERR("I2C ch%d:0x%X reset cause %d",
1033 config->port, data->addr_16bit, I2C_RC_TIMEOUT);
1034 /* If this message is sent fail, drop the transaction. */
1035 break;
1036 }
1037
1038 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1039 /*
1040 * In FIFO mode, messages are compressed into a single
1041 * transaction.
1042 */
1043 if (fifo_mode_enable) {
1044 break;
1045 }
1046 #endif
1047 }
1048 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1049 if (fifo_mode_enable) {
1050 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
1051
1052 /* Disable SMB channels in FIFO mode. */
1053 *reg_mstfctrl &= ~IT8XXX2_SMB_FFEN;
1054 /* Disable I2C write to read FIFO mode. */
1055 if (data->num_msgs == 2) {
1056 i2c_fifo_en_w2r(dev, 0);
1057 }
1058 /* Permit to enter power policy. */
1059 pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
1060 }
1061 #endif
1062 /* reset i2c channel status */
1063 if (data->err || (data->active_msg->flags & I2C_MSG_STOP)) {
1064 data->i2ccs = I2C_CH_NORMAL;
1065 }
1066 /* Save return value. */
1067 ret = i2c_parsing_return_value(dev);
1068 /* Unlock mutex of i2c controller */
1069 k_mutex_unlock(&data->mutex);
1070
1071 return ret;
1072 }
1073
i2c_it8xxx2_isr(const struct device * dev)1074 static void i2c_it8xxx2_isr(const struct device *dev)
1075 {
1076 struct i2c_it8xxx2_data *data = dev->data;
1077 const struct i2c_it8xxx2_config *config = dev->config;
1078
1079 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1080 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
1081
1082 /* If done doing work, wake up the task waiting for the transfer. */
1083 if (config->fifo_enable && (*reg_mstfctrl & IT8XXX2_SMB_FFEN)) {
1084 if (i2c_fifo_transaction(dev)) {
1085 return;
1086 }
1087 } else
1088 #endif
1089 {
1090 if (i2c_pio_transaction(dev)) {
1091 return;
1092 }
1093 }
1094 irq_disable(config->i2c_irq_base);
1095 k_sem_give(&data->device_sync_sem);
1096 }
1097
i2c_it8xxx2_init(const struct device * dev)1098 static int i2c_it8xxx2_init(const struct device *dev)
1099 {
1100 struct i2c_it8xxx2_data *data = dev->data;
1101 const struct i2c_it8xxx2_config *config = dev->config;
1102 uint8_t *base = config->base;
1103 uint32_t bitrate_cfg;
1104 int error, status;
1105
1106 /* Initialize mutex and semaphore */
1107 k_mutex_init(&data->mutex);
1108 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
1109
1110 /* Enable clock to specified peripheral */
1111 volatile uint8_t *reg = (volatile uint8_t *)
1112 (IT8XXX2_ECPM_BASE + (config->clock_gate_offset >> 8));
1113 uint8_t reg_mask = config->clock_gate_offset & 0xff;
1114 *reg &= ~reg_mask;
1115
1116 /* Enable SMBus function */
1117 /*
1118 * bit0, The SMBus host interface is enabled.
1119 * bit1, Enable to communicate with I2C device
1120 * and support I2C-compatible cycles.
1121 * bit4, This bit controls the reset mechanism
1122 * of SMBus master to handle the SMDAT
1123 * line low if 25ms reg timeout.
1124 */
1125 IT8XXX2_SMB_HOCTL2(base) = IT8XXX2_SMB_SMD_TO_EN | IT8XXX2_SMB_SMHEN;
1126 /*
1127 * bit1, Kill SMBus host transaction.
1128 * bit0, Enable the interrupt for the master interface.
1129 */
1130 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_KILL | IT8XXX2_SMB_SMHEN;
1131 IT8XXX2_SMB_HOCTL(base) = IT8XXX2_SMB_SMHEN;
1132
1133 /* W/C host status register */
1134 IT8XXX2_SMB_HOSTA(base) = HOSTA_ALL_WC_BIT;
1135 IT8XXX2_SMB_HOCTL2(base) = 0x00;
1136
1137 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1138 volatile uint8_t *reg_mstfctrl = config->reg_mstfctrl;
1139
1140 if (config->port == SMB_CHANNEL_B && config->fifo_enable) {
1141 /* Select channel B in FIFO2. */
1142 *reg_mstfctrl = IT8XXX2_SMB_FFCHSEL2_B;
1143 } else if (config->port == SMB_CHANNEL_C && config->fifo_enable) {
1144 /* Select channel C in FIFO2. */
1145 *reg_mstfctrl = IT8XXX2_SMB_FFCHSEL2_C;
1146 }
1147 #endif
1148
1149 /* ChannelA-C switch selection of I2C pin */
1150 if (config->port == SMB_CHANNEL_A) {
1151 IT8XXX2_SMB_SMB01CHS = (IT8XXX2_SMB_SMB01CHS &= ~GENMASK(2, 0)) |
1152 config->channel_switch_sel;
1153 } else if (config->port == SMB_CHANNEL_B) {
1154 IT8XXX2_SMB_SMB01CHS = (config->channel_switch_sel << 4) |
1155 (IT8XXX2_SMB_SMB01CHS &= ~GENMASK(6, 4));
1156 } else if (config->port == SMB_CHANNEL_C) {
1157 IT8XXX2_SMB_SMB23CHS = (IT8XXX2_SMB_SMB23CHS &= ~GENMASK(2, 0)) |
1158 config->channel_switch_sel;
1159 }
1160
1161 /* Set clock frequency for I2C ports */
1162 if (config->bitrate == I2C_BITRATE_STANDARD ||
1163 config->bitrate == I2C_BITRATE_FAST ||
1164 config->bitrate == I2C_BITRATE_FAST_PLUS) {
1165 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
1166 } else {
1167 /* Device tree specified speed */
1168 bitrate_cfg = I2C_SPEED_DT << I2C_SPEED_SHIFT;
1169 }
1170
1171 error = i2c_it8xxx2_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
1172 data->i2ccs = I2C_CH_NORMAL;
1173
1174 if (error) {
1175 LOG_ERR("i2c: failure initializing");
1176 return error;
1177 }
1178
1179 /* Set the pin to I2C alternate function. */
1180 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1181 if (status < 0) {
1182 LOG_ERR("Failed to configure I2C pins");
1183 return status;
1184 }
1185
1186 return 0;
1187 }
1188
i2c_it8xxx2_recover_bus(const struct device * dev)1189 static int i2c_it8xxx2_recover_bus(const struct device *dev)
1190 {
1191 const struct i2c_it8xxx2_config *config = dev->config;
1192 int i, status;
1193
1194 /* Output type selection */
1195 gpio_flags_t flags = GPIO_OUTPUT | (config->push_pull_recovery ? 0 : GPIO_OPEN_DRAIN);
1196 /* Set SCL of I2C as GPIO pin */
1197 gpio_pin_configure_dt(&config->scl_gpios, flags);
1198 /* Set SDA of I2C as GPIO pin */
1199 gpio_pin_configure_dt(&config->sda_gpios, flags);
1200
1201 /*
1202 * In I2C recovery bus, 1ms sleep interval for bitbanging i2c
1203 * is mainly to ensure that gpio has enough time to go from
1204 * low to high or high to low.
1205 */
1206 /* Pull SCL and SDA pin to high */
1207 gpio_pin_set_dt(&config->scl_gpios, 1);
1208 gpio_pin_set_dt(&config->sda_gpios, 1);
1209 k_msleep(1);
1210
1211 /* Start condition */
1212 gpio_pin_set_dt(&config->sda_gpios, 0);
1213 k_msleep(1);
1214 gpio_pin_set_dt(&config->scl_gpios, 0);
1215 k_msleep(1);
1216
1217 /* 9 cycles of SCL with SDA held high */
1218 for (i = 0; i < 9; i++) {
1219 /* SDA */
1220 gpio_pin_set_dt(&config->sda_gpios, 1);
1221 /* SCL */
1222 gpio_pin_set_dt(&config->scl_gpios, 1);
1223 k_msleep(1);
1224 /* SCL */
1225 gpio_pin_set_dt(&config->scl_gpios, 0);
1226 k_msleep(1);
1227 }
1228 /* SDA */
1229 gpio_pin_set_dt(&config->sda_gpios, 0);
1230 k_msleep(1);
1231
1232 /* Stop condition */
1233 gpio_pin_set_dt(&config->scl_gpios, 1);
1234 k_msleep(1);
1235 gpio_pin_set_dt(&config->sda_gpios, 1);
1236 k_msleep(1);
1237
1238 /* Set GPIO back to I2C alternate function of SCL */
1239 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
1240 if (status < 0) {
1241 LOG_ERR("Failed to configure I2C pins");
1242 return status;
1243 }
1244
1245 /* reset i2c port */
1246 i2c_reset(dev);
1247 LOG_ERR("I2C ch%d reset cause %d", config->port,
1248 I2C_RC_NO_IDLE_FOR_START);
1249
1250 return 0;
1251 }
1252
1253 static const struct i2c_driver_api i2c_it8xxx2_driver_api = {
1254 .configure = i2c_it8xxx2_configure,
1255 .get_config = i2c_it8xxx2_get_config,
1256 .transfer = i2c_it8xxx2_transfer,
1257 .recover_bus = i2c_it8xxx2_recover_bus,
1258 };
1259
1260 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
1261 /*
1262 * Sometimes, channel C may write wrong register to the target device.
1263 * This issue occurs when FIFO2 is enabled on channel C. The problem
1264 * arises because FIFO2 is shared between channel B and channel C.
1265 * FIFO2 will be disabled when data access is completed, at which point
1266 * FIFO2 is set to the default configuration for channel B.
1267 * The byte counter of FIFO2 may be affected by channel B. There is a chance
1268 * that channel C may encounter wrong register being written due to FIFO2
1269 * byte counter wrong write after channel B's write operation.
1270 */
1271 BUILD_ASSERT((DT_PROP(DT_NODELABEL(i2c2), fifo_enable) == false),
1272 "Channel C cannot use FIFO mode.");
1273 #endif
1274
1275 #ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
1276 #define I2C_IT8XXX2_CHECK_SUPPORTED_CLOCK(inst) \
1277 BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) == \
1278 I2C_BITRATE_FAST), "Only supports 400 KHz");
1279
1280 DT_INST_FOREACH_STATUS_OKAY(I2C_IT8XXX2_CHECK_SUPPORTED_CLOCK)
1281 #endif
1282
1283 #define I2C_ITE_IT8XXX2_INIT(inst) \
1284 PINCTRL_DT_INST_DEFINE(inst); \
1285 BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) == \
1286 50000) || \
1287 (DT_INST_PROP(inst, clock_frequency) == \
1288 I2C_BITRATE_STANDARD) || \
1289 (DT_INST_PROP(inst, clock_frequency) == \
1290 I2C_BITRATE_FAST) || \
1291 (DT_INST_PROP(inst, clock_frequency) == \
1292 I2C_BITRATE_FAST_PLUS), "Not support I2C bit rate value"); \
1293 static void i2c_it8xxx2_config_func_##inst(void); \
1294 \
1295 static const struct i2c_it8xxx2_config i2c_it8xxx2_cfg_##inst = { \
1296 .base = (uint8_t *)(DT_INST_REG_ADDR_BY_IDX(inst, 0)), \
1297 .reg_mstfctrl = (uint8_t *)(DT_INST_REG_ADDR_BY_IDX(inst, 1)), \
1298 .irq_config_func = i2c_it8xxx2_config_func_##inst, \
1299 .bitrate = DT_INST_PROP(inst, clock_frequency), \
1300 .i2c_irq_base = DT_INST_IRQN(inst), \
1301 .port = DT_INST_PROP(inst, port_num), \
1302 .channel_switch_sel = DT_INST_PROP(inst, channel_switch_sel), \
1303 .scl_gpios = GPIO_DT_SPEC_INST_GET(inst, scl_gpios), \
1304 .sda_gpios = GPIO_DT_SPEC_INST_GET(inst, sda_gpios), \
1305 .clock_gate_offset = DT_INST_PROP(inst, clock_gate_offset), \
1306 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst), \
1307 .fifo_enable = DT_INST_PROP(inst, fifo_enable), \
1308 .push_pull_recovery = DT_INST_PROP(inst, push_pull_recovery), \
1309 }; \
1310 \
1311 static struct i2c_it8xxx2_data i2c_it8xxx2_data_##inst; \
1312 \
1313 I2C_DEVICE_DT_INST_DEFINE(inst, i2c_it8xxx2_init, \
1314 NULL, \
1315 &i2c_it8xxx2_data_##inst, \
1316 &i2c_it8xxx2_cfg_##inst, \
1317 POST_KERNEL, \
1318 CONFIG_I2C_INIT_PRIORITY, \
1319 &i2c_it8xxx2_driver_api); \
1320 \
1321 static void i2c_it8xxx2_config_func_##inst(void) \
1322 { \
1323 IRQ_CONNECT(DT_INST_IRQN(inst), \
1324 0, \
1325 i2c_it8xxx2_isr, \
1326 DEVICE_DT_INST_GET(inst), 0); \
1327 }
1328
1329 DT_INST_FOREACH_STATUS_OKAY(I2C_ITE_IT8XXX2_INIT)
1330
