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Searched refs:i0 (Results 1 – 8 of 8) sorted by relevance

/Zephyr-Core-3.7.0/arch/sparc/core/
Dsw_trap_set_pil.S30 sll %i0, PSR_PIL_BIT, %i0
32 or %l5, %i0, %l5
40 srl %l3, PSR_PIL_BIT, %i0
Dswitch.S39 std %i0, [%o1 + _thread_offset_to_i0]
77 std %i0, [%sp + 0x20]
127 ldd [%o0 + _thread_offset_to_i0], %i0
153 mov %i0, %o0
Dwindow_trap.S33 std %i0, [%sp + 0x20]
69 ldd [%sp + 0x20], %i0
119 std %i0, [%sp + 0x20]
Dfault_trap.S63 std %i0, [%sp + 0x20]
84 std %i0, [%sp + 96 + __struct_arch_esf_out_OFFSET + 0x00]
Dthread.c40 thread->callee_saved.i0 = (uint32_t) entry; in arch_new_thread()
Dinterrupt_trap.S69 std %i0, [%sp + 0x20]
315 ldd [%g1 + 0x20], %i0
/Zephyr-Core-3.7.0/include/zephyr/arch/sparc/
Dthread.h52 uint32_t i0; member
/Zephyr-Core-3.7.0/arch/sparc/core/offsets/
Doffsets.c27 GEN_OFFSET_SYM(_callee_saved_t, i0);