Searched refs:hclk_div_ratio (Results 1 – 2 of 2) sorted by relevance
37 uint32_t hclk_div_ratio, bclk_div_ratio; in esai_get_clock_rate_config() local72 hclk_div_ratio = 1; in esai_get_clock_rate_config()93 hclk_div_ratio = DIV_ROUND_UP(extal_rate, hclk_rate); in esai_get_clock_rate_config()95 if (hclk_div_ratio > 256) { in esai_get_clock_rate_config()102 hclk_div_ratio = DIV_ROUND_UP(extal_rate, hclk_rate); in esai_get_clock_rate_config()104 if (hclk_div_ratio > 256) { in esai_get_clock_rate_config()113 cfg->hclk_div_ratio = hclk_div_ratio; in esai_get_clock_rate_config()119 extal_rate = DIV_ROUND_UP(extal_rate, hclk_div_ratio); in esai_get_clock_rate_config()126 hclk_div_ratio = DIV_ROUND_UP(extal_rate, bclk_rate); in esai_get_clock_rate_config()129 if (hclk_div_ratio > 256 * 16) { in esai_get_clock_rate_config()[all …]
213 uint32_t hclk_div_ratio; member487 LOG_DBG("HCLK divider ratio: %d", cfg->hclk_div_ratio); in esai_dump_xceiver_config()
