| /Zephyr-Core-3.7.0/drivers/clock_control/ |
| D | clock_control_renesas_cpg_mssr.c | 136 int64_t freq = -ENOTSUP; in rcar_cpg_get_in_update_out_freq() local
140 return freq; in rcar_cpg_get_in_update_out_freq()
146 return freq; in rcar_cpg_get_in_update_out_freq()
154 freq = rcar_cpg_get_in_update_out_freq(dev, parent_clk); in rcar_cpg_get_in_update_out_freq()
155 if (freq < 0) { in rcar_cpg_get_in_update_out_freq()
156 return freq; in rcar_cpg_get_in_update_out_freq()
161 freq = rcar_cpg_update_out_freq(dev, clk_info); in rcar_cpg_get_in_update_out_freq()
162 if (freq < 0) { in rcar_cpg_get_in_update_out_freq()
163 return freq; in rcar_cpg_get_in_update_out_freq()
171 int64_t freq; in rcar_cpg_get_out_freq() local
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| D | beetle_clock_control.c | 29 uint32_t freq; member
138 uint32_t nc_mainclk = beetle_round_freq(cfg->freq); in beetle_clock_control_get_subsys_rate()
229 if (cfg->freq != MAINCLK_BASE_FREQ) { in beetle_clock_control_init()
230 beetle_pll_enable(cfg->freq); in beetle_clock_control_init()
239 .freq = DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency),
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| D | clock_control_litex.c | 345 ldev->g_config.freq = f; in litex_clk_get_real_global_frequency()
348 ldev->ts_g_config.freq = ldev->g_config.freq; in litex_clk_get_real_global_frequency()
441 lcko->def.freq, lcko->def.duty.num, in litex_clk_print_params()
445 lcko->ts_config.div, lcko->ts_config.freq, in litex_clk_print_params()
450 lcko->config.div, lcko->config.freq, in litex_clk_print_params()
472 ldev->ts_g_config.freq, ldev->ts_g_config.mul, in litex_clk_print_all_params()
476 ldev->g_config.freq, ldev->g_config.mul, ldev->g_config.div); in litex_clk_print_all_params()
824 ldev->g_config.freq = ldev->ts_g_config.freq; in litex_clk_set_globs()
1262 m = lcko->ts_config.freq * lcko->margin.m; in litex_clk_calc_clkout_params()
1268 delta_f = clk_freq - lcko->ts_config.freq; in litex_clk_calc_clkout_params()
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| /Zephyr-Core-3.7.0/drivers/sensor/wsen/wsen_itds/ |
| D | itds.c | 37 uint16_t *freq, uint16_t *mfreq) in itds_get_odr_for_index() argument
57 *freq = itds_odr_map[idx].freq; in itds_get_odr_for_index()
63 static int itds_accl_odr_set(const struct device *dev, uint16_t freq, in itds_accl_odr_set() argument
81 if ((freq == itds_odr_map[i].freq) && in itds_accl_odr_set()
319 uint16_t freq, mfreq; in itds_init() local
361 ret = itds_get_odr_for_index(dev, cfg->def_odr, &freq, &mfreq); in itds_init()
367 ret = itds_accl_odr_set(dev, freq, mfreq); in itds_init()
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| /Zephyr-Core-3.7.0/drivers/pwm/ |
| D | pwm_led_esp32.c | 34 uint32_t freq; member
132 uint32_t max_precision_n = clock_freq/channel->freq; in pwm_led_esp32_calculate_max_resolution()
200 __ASSERT_NO_MSG(channel->freq > 0); in pwm_led_esp32_timer_set()
209 prescaler = ((uint64_t) APB_CLK_FREQ << 8) / channel->freq / precision; in pwm_led_esp32_timer_set()
214 prescaler = ((uint64_t) SCLK_CLK_FREQ << 8) / channel->freq / precision; in pwm_led_esp32_timer_set()
219 prescaler = ((uint64_t) REF_CLK_FREQ << 8) / channel->freq / precision; in pwm_led_esp32_timer_set()
291 channel->freq = (uint32_t) (clk_freq/period_cycles); in pwm_led_esp32_set_cycles()
292 if (!channel->freq) { in pwm_led_esp32_set_cycles()
293 channel->freq = 1; in pwm_led_esp32_set_cycles()
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| D | pwm_xlnx_axi_timer.c | 45 uint32_t freq; member
170 *cycles = config->freq; in xlnx_axi_timer_get_cycles_per_sec()
193 .freq = DT_INST_PROP(n, clock_frequency), \
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| /Zephyr-Core-3.7.0/modules/hal_nordic/nrfs/dvfs/ |
| D | ld_dvfs_handler.c | 191 if (dvfs_service_handler_is_downscaling(p_evt->freq)) { in nrfs_dvfs_evt_handler()
193 dvfs_service_handler_prepare_to_scale(p_evt->freq); in nrfs_dvfs_evt_handler()
196 dvfs_service_handler_scaling_background_job(p_evt->freq); in nrfs_dvfs_evt_handler()
199 current_freq_setting = p_evt->freq; in nrfs_dvfs_evt_handler()
208 dvfs_service_handler_scaling_finish(p_evt->freq); in nrfs_dvfs_evt_handler()
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| /Zephyr-Core-3.7.0/drivers/i2c/ |
| D | i2c_gd32.c | 495 uint32_t pclk1, freq, clkc; in i2c_gd32_configure() local
508 freq = pclk1 / 1000000U; in i2c_gd32_configure()
509 if (freq > I2CCLK_MAX) { in i2c_gd32_configure()
511 I2CCLK_MAX, freq); in i2c_gd32_configure()
547 if (freq < I2CCLK_MIN) { in i2c_gd32_configure()
549 I2CCLK_MIN, freq); in i2c_gd32_configure()
554 I2C_CTL1(cfg->reg) |= freq; in i2c_gd32_configure()
557 if (freq == I2CCLK_MAX) { in i2c_gd32_configure()
560 I2C_RT(cfg->reg) = freq + 1U; in i2c_gd32_configure()
573 if (freq < I2CCLK_FM_MIN) { in i2c_gd32_configure()
[all …]
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| /Zephyr-Core-3.7.0/tests/drivers/spi/spi_loopback/boards/ |
| D | nucleo_h723zg.overlay | 7 /* Set div-q to get test clk freq into acceptable SPI freq range */
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| D | nucleo_h743zi.overlay | 9 /* Set div-q to get test clk freq into acceptable SPI freq range */
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| D | nucleo_h753zi.overlay | 9 /* Set div-q to get test clk freq into acceptable SPI freq range */
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| /Zephyr-Core-3.7.0/drivers/counter/ |
| D | counter_mcux_qtmr.c | 43 uint32_t freq; member
254 return data->freq; in mcux_qtmr_get_freq()
270 data->freq = config->info.freq; in mcux_qtmr_init()
279 &data->freq)) { in mcux_qtmr_init()
283 data->freq /= qtmr_primary_source_divider[config->qtmr_config.primarySource - in mcux_qtmr_init()
314 .freq = DT_INST_PROP_OR(n, freq, 0), \
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| D | counter_dw_timer.c | 49 uint32_t freq; member
72 uint32_t freq; member
292 return data->freq; in counter_dw_timer_get_freq()
296 return config->freq; in counter_dw_timer_get_freq()
331 timer_config->clkid, &data->freq); in counter_dw_timer_init()
362 .freq = DT_INST_PROP(inst, clock_frequency), \
365 .freq = 0, \
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| /Zephyr-Core-3.7.0/tests/drivers/spi/spi_loopback/ |
| D | overlay-stm32-spi-16bits.overlay | 7 /* Set div-q to get test clk freq into acceptable SPI freq range */
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| /Zephyr-Core-3.7.0/drivers/ieee802154/ |
| D | ieee802154_cc1200.c | 224 static bool write_reg_freq(const struct device *dev, uint32_t freq) in write_reg_freq() argument
228 freq_data[0] = (uint8_t)((freq & 0x00FF0000) >> 16); in write_reg_freq()
229 freq_data[1] = (uint8_t)((freq & 0x0000FF00) >> 8); in write_reg_freq()
230 freq_data[2] = (uint8_t)(freq & 0x000000FF); in write_reg_freq()
272 uint32_t freq = 0U; in rf_evaluate_freq_setting() local
304 freq += freq_tmp; in rf_evaluate_freq_setting()
312 LOG_DBG("FREQ is 0x%06X", freq); in rf_evaluate_freq_setting()
314 return freq; in rf_evaluate_freq_setting()
547 uint32_t freq; in cc1200_set_channel() local
569 freq = rf_evaluate_freq_setting(dev, channel); in cc1200_set_channel()
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| /Zephyr-Core-3.7.0/tests/boards/espressif_esp32/rtc_clk/ |
| D | README.rst | 68 Testing RTC FAST CLK freq: 20000000 MHz
69 Testing RTC FAST CLK freq: 17500000 MHz
73 Testing RTC SLOW CLK freq: 136000 MHz
74 Testing RTC SLOW CLK freq: 68359 MHz
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| /Zephyr-Core-3.7.0/drivers/sensor/st/lsm6dso16is/ |
| D | lsm6dso16is_shub.c | 84 uint8_t i2c_addr, uint16_t freq) in lsm6dso16is_lis2mdl_odr_set() argument
89 if (freq <= lis2mdl_map[odr]) { in lsm6dso16is_lis2mdl_odr_set()
95 LOG_DBG("shub: LIS2MDL freq val %d not supported.", freq); in lsm6dso16is_lis2mdl_odr_set()
180 uint8_t i2c_addr, uint16_t freq) in lsm6dso16is_hts221_odr_set() argument
185 if (freq <= hts221_map[odr]) { in lsm6dso16is_hts221_odr_set()
191 LOG_DBG("shub: HTS221 freq val %d not supported.", freq); in lsm6dso16is_hts221_odr_set()
293 uint8_t i2c_addr, uint16_t freq) in lsm6dso16is_lps22hh_odr_set() argument
298 if (freq <= lps22hh_map[odr]) { in lsm6dso16is_lps22hh_odr_set()
304 LOG_DBG("shub: LPS22HH freq val %d not supported.", freq); in lsm6dso16is_lps22hh_odr_set()
373 uint8_t i2c_addr, uint16_t freq) in lsm6dso16is_lps22df_odr_set() argument
[all …]
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| /Zephyr-Core-3.7.0/drivers/sensor/st/lsm6dsv16x/ |
| D | lsm6dsv16x_shub.c | 84 uint8_t i2c_addr, uint16_t freq) in lsm6dsv16x_lis2mdl_odr_set() argument
89 if (freq <= lis2mdl_map[odr]) { in lsm6dsv16x_lis2mdl_odr_set()
95 LOG_DBG("shub: LIS2MDL freq val %d not supported.", freq); in lsm6dsv16x_lis2mdl_odr_set()
180 uint8_t i2c_addr, uint16_t freq) in lsm6dsv16x_hts221_odr_set() argument
185 if (freq <= hts221_map[odr]) { in lsm6dsv16x_hts221_odr_set()
191 LOG_DBG("shub: HTS221 freq val %d not supported.", freq); in lsm6dsv16x_hts221_odr_set()
293 uint8_t i2c_addr, uint16_t freq) in lsm6dsv16x_lps22hh_odr_set() argument
298 if (freq <= lps22hh_map[odr]) { in lsm6dsv16x_lps22hh_odr_set()
304 LOG_DBG("shub: LPS22HH freq val %d not supported.", freq); in lsm6dsv16x_lps22hh_odr_set()
373 uint8_t i2c_addr, uint16_t freq) in lsm6dsv16x_lps22df_odr_set() argument
[all …]
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| /Zephyr-Core-3.7.0/modules/hostap/src/ |
| D | supp_api.c | 225 mode->channels[i].freq); in wpa_supp_supported_channels()
246 return mode->channels[i].freq; in wpa_supp_band_chan_compat()
272 int freq = -1; in chan_to_freq() local
277 freq = ieee80211_chan_to_freq(NULL, op_classes[i], chan); in chan_to_freq()
278 if (freq > 0) { in chan_to_freq()
283 if (freq <= 0) { in chan_to_freq()
288 return freq; in chan_to_freq()
461 int freq; in wpas_add_and_config_network() local
464 freq = wpa_supp_band_chan_compat(wpa_s, params->band, params->channel); in wpas_add_and_config_network()
465 if (freq < 0) { in wpas_add_and_config_network()
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| /Zephyr-Core-3.7.0/dts/xtensa/intel/ |
| D | intel_adsp_cavs18.dtsi | 58 adsp-clkctl-freq-enc = <0x20000002 0x80000006>;
59 adsp-clkctl-freq-mask = <0x20000000 0x80000000>;
60 adsp-clkctl-freq-default = <1>;
61 adsp-clkctl-freq-lowest = <0>;
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| D | intel_adsp_cavs20.dtsi | 58 adsp-clkctl-freq-enc = <0x20000002 0x80000006>;
59 adsp-clkctl-freq-mask = <0x20000000 0x80000000>;
60 adsp-clkctl-freq-default = <1>;
61 adsp-clkctl-freq-lowest = <0>;
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| /Zephyr-Core-3.7.0/boards/gaisler/gr716a_mini/ |
| D | board.cmake | 7 set(TSIM_SYS -freq 20 -gr716)
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| /Zephyr-Core-3.7.0/drivers/sensor/st/lsm9ds1/ |
| D | lsm9ds1.c | 99 static int lsm9ds1_accel_freq_to_odr_val(uint16_t freq) in lsm9ds1_accel_freq_to_odr_val() argument
104 if (freq <= lsm9ds1_odr_map[i]) { in lsm9ds1_accel_freq_to_odr_val()
112 static int lsm9ds1_gyro_freq_to_odr_val(uint16_t freq) in lsm9ds1_gyro_freq_to_odr_val() argument
117 if (freq <= lsm9ds1_gyro_odr_map[i]) { in lsm9ds1_gyro_freq_to_odr_val()
176 static int lsm9ds1_gyro_odr_set(const struct device *dev, uint16_t freq) in lsm9ds1_gyro_odr_set() argument
182 odr = lsm9ds1_gyro_freq_to_odr_val(freq); in lsm9ds1_gyro_odr_set()
210 static int lsm9ds1_accel_odr_set(const struct device *dev, uint16_t freq) in lsm9ds1_accel_odr_set() argument
229 odr = lsm9ds1_gyro_freq_to_odr_val(freq); in lsm9ds1_accel_odr_set()
252 odr = lsm9ds1_accel_freq_to_odr_val(freq); in lsm9ds1_accel_odr_set()
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| /Zephyr-Core-3.7.0/subsys/testsuite/busy_sim/ |
| D | busy_sim.c | 171 uint32_t freq; in busy_sim_init() local
187 freq = counter_get_frequency(config->counter); in busy_sim_init()
188 if (freq < 1000000) { in busy_sim_init()
198 data->us_tick = freq / 1000000; in busy_sim_init()
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| /Zephyr-Core-3.7.0/soc/snps/arc_iot/ |
| D | sysconf.c | 76 int32_t arc_iot_pll_fout_config(uint32_t freq) in arc_iot_pll_fout_config() argument
80 if (freq == PLL_CLK_IN) { in arc_iot_pll_fout_config()
85 if (pll_configuration[i].fout == freq) { in arc_iot_pll_fout_config()
95 if (freq > 100) { in arc_iot_pll_fout_config()
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