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Searched refs:dmic_base (Results 1 – 2 of 2) sorted by relevance

/Zephyr-Core-3.7.0/drivers/dai/intel/dmic/
Ddmic.c28 static const uint32_t dmic_base[4] = {PDM0, PDM1, PDM2, PDM3}; variable
518 dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, in dai_dmic_gain_ramp()
522 dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE * in dai_dmic_gain_ramp()
529 dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE * in dai_dmic_gain_ramp()
531 dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE * in dai_dmic_gain_ramp()
534 dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE * in dai_dmic_gain_ramp()
537 dai_dmic_write(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE * in dai_dmic_gain_ramp()
559 dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, CIC_CONTROL_SOFT_RESET, 0); in dai_dmic_start()
585 dai_dmic_update_bits(dmic, dmic_base[i] + CIC_CONTROL, in dai_dmic_start()
590 dai_dmic_update_bits(dmic, dmic_base[i] + MIC_CONTROL, in dai_dmic_start()
[all …]
Ddmic_nhlt.c24 static const uint32_t dmic_base[4] = {PDM0, PDM1, PDM2, PDM3}; variable
134 val = dai_dmic_read(dmic, dmic_base[pdm] + CIC_CONFIG); in dai_nhlt_get_clock_div()
137 val = dai_dmic_read(dmic, dmic_base[pdm] + MIC_CONTROL); in dai_nhlt_get_clock_div()
140 val = dai_dmic_read(dmic, dmic_base[pdm] + in dai_nhlt_get_clock_div()
191 dmic, dmic_base[source_pdm] + MIC_CONTROL)); in dai_ipm_source_to_enable()
360 fir_control[0] = dai_dmic_read(dmic, dmic_base[0] + in dai_nhlt_dmic_dai_params_get()
364 fir_control[1] = dai_dmic_read(dmic, dmic_base[1] + in dai_nhlt_dmic_dai_params_get()
368 mic_control[0] = dai_dmic_read(dmic, dmic_base[0] + MIC_CONTROL); in dai_nhlt_dmic_dai_params_get()
369 mic_control[1] = dai_dmic_read(dmic, dmic_base[1] + MIC_CONTROL); in dai_nhlt_dmic_dai_params_get()
727 pdm_base = dmic_base[pdm_idx]; in dai_dmic_set_config_nhlt()