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Searched refs:div_mask (Results 1 – 4 of 4) sorted by relevance

/Zephyr-Core-3.7.0/drivers/clock_control/
Dclock_control_r8a779f0_cpg_mssr.c202 static int r8a779f0_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask) in r8a779f0_set_rate_helper() argument
211 *div_mask = R8A779F0_CLK_SDSRC_DIV_MASK << R8A779F0_CLK_SDSRC_DIV_SHIFT; in r8a779f0_set_rate_helper()
220 *div_mask = R8A779F0_CLK_SD0_DIV_MASK << R8A779F0_CLK_SD0_DIV_SHIFT; in r8a779f0_set_rate_helper()
231 *div_mask = R8A779F0_CLK_SD0H_DIV_MASK << R8A779F0_CLK_SD0H_DIV_SHIFT; in r8a779f0_set_rate_helper()
Dclock_control_r8a7795_cpg_mssr.c204 static int r8a7795_set_rate_helper(uint32_t module, uint32_t *divider, uint32_t *div_mask) in r8a7795_set_rate_helper() argument
215 *div_mask = R8A7795_CLK_SD_DIV_MASK << R8A7795_CLK_SD_DIV_SHIFT; in r8a7795_set_rate_helper()
231 *div_mask = R8A7795_CLK_SDH_DIV_MASK << R8A7795_CLK_SDH_DIV_SHIFT; in r8a7795_set_rate_helper()
237 *div_mask = R8A7795_CLK_CANFD_DIV_MASK; in r8a7795_set_rate_helper()
Dclock_control_renesas_cpg_mssr.h43 int (*set_rate_helper)(uint32_t module, uint32_t *div, uint32_t *div_mask);
Dclock_control_renesas_cpg_mssr.c268 uint32_t div_mask; in rcar_cpg_set_rate() local
313 ret = data->set_rate_helper(module, &divider, &div_mask); in rcar_cpg_set_rate()
318 reg &= ~div_mask; in rcar_cpg_set_rate()