Searched refs:csr_set (Results 1 – 8 of 8) sorted by relevance
| /Zephyr-Core-3.7.0/arch/riscv/core/ |
| D | fpu.c | 88 csr_set(mstatus, MSTATUS_FS_INIT); in z_riscv_fpu_load()
115 csr_set(mstatus, MSTATUS_FS_CLEAN); in arch_flush_local_fpu()
316 csr_set(mstatus, _current_cpu->arch.fpu_state); in z_riscv_fpu_thread_context_switch()
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| D | pmp.c | 395 csr_set(mstatus, MSTATUS_MPRV); in z_riscv_pmp_init()
511 csr_set(mstatus, MSTATUS_MPRV); in z_riscv_pmp_stackguard_enable()
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| /Zephyr-Core-3.7.0/drivers/cache/ |
| D | cache_andes.c | 213 csr_set(NDS_MCACHE_CTL, MCACHE_CTL_DC_COHEN); in cache_data_enable()
224 csr_set(NDS_MCACHE_CTL, MCACHE_CTL_DC_EN); in cache_data_enable()
272 csr_set(NDS_MCACHE_CTL, MCACHE_CTL_IC_EN); in cache_instr_enable()
543 csr_set(NDS_MCACHE_CTL, MCACHE_CTL_CCTL_SUEN); in andes_cache_init()
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| /Zephyr-Core-3.7.0/include/zephyr/arch/riscv/ |
| D | csr.h | 211 #define csr_set(csr, val) \ macro
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| /Zephyr-Core-3.7.0/drivers/interrupt_controller/ |
| D | intc_ite_it8xxx2_v2.c | 265 csr_set(mie, MIP_MEIP); in soc_interrupt_init()
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| D | intc_ite_it8xxx2.c | 275 csr_set(mie, MIP_MEIP); in soc_interrupt_init()
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| /Zephyr-Core-3.7.0/soc/ite/ec/it8xxx2/ |
| D | soc.c | 264 csr_set(mie, MIP_MEIP); in riscv_idle()
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| /Zephyr-Core-3.7.0/tests/arch/riscv/fpu_sharing/src/ |
| D | main.c | 273 csr_set(mstatus, MSTATUS_IEN); in exception_context()
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