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Searched refs:clock_dev (Results 1 – 25 of 94) sorted by relevance

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/Zephyr-Core-3.7.0/drivers/dac/
Ddac_esp32.c23 const struct device *clock_dev; member
56 if (!cfg->clock_dev) { in dac_esp32_init()
61 if (!device_is_ready(cfg->clock_dev)) { in dac_esp32_init()
66 if (clock_control_on(cfg->clock_dev, in dac_esp32_init()
84 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
/Zephyr-Core-3.7.0/tests/drivers/clock_control/nrf_onoff_and_bt/src/
Dmain.c22 static const struct device *const clock_dev = DEVICE_DT_GET_ONE(nordic_nrf_clock); variable
30 zassert_true(device_is_ready(clock_dev)); in setup()
124 check_hf_status(clock_dev, true, true); in ZTEST()
139 check_hf_status(clock_dev, false, true); in ZTEST()
210 check_hf_status(clock_dev, true, false); in ZTEST()
224 check_hf_status(clock_dev, false, true); in ZTEST()
/Zephyr-Core-3.7.0/drivers/pinctrl/
Dpinctrl_kinetis.c38 const struct device *clock_dev; member
64 if (!device_is_ready(config->clock_dev)) { in pinctrl_mcux_init()
69 err = clock_control_on(config->clock_dev, config->clock_subsys); in pinctrl_mcux_init()
89 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-Core-3.7.0/drivers/ethernet/eth_nxp_enet_qos/
Deth_nxp_enet_qos.c22 ret = clock_control_on(config->clock_dev, config->clock_subsys); in nxp_enet_qos_init()
35 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-Core-3.7.0/drivers/pwm/
Dpwm_mcux_tpm.c29 const struct device *clock_dev; member
145 if (!device_is_ready(config->clock_dev)) { in mcux_tpm_init()
150 if (clock_control_on(config->clock_dev, config->clock_subsys)) { in mcux_tpm_init()
155 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_tpm_init()
192 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dpwm_rv32m1_tpm.c28 const struct device *clock_dev; member
144 if (!device_is_ready(config->clock_dev)) { in rv32m1_tpm_init()
149 if (clock_control_on(config->clock_dev, config->clock_subsys)) { in rv32m1_tpm_init()
154 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in rv32m1_tpm_init()
191 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dpwm_mcux.c26 const struct device *clock_dev; member
63 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_pwm_set_cycles_internal()
181 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_pwm_get_cycles_per_sec()
200 if (!device_is_ready(config->clock_dev)) { in pwm_mcux_init()
257 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dpwm_mcux_sctimer.c30 const struct device *clock_dev; member
53 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_sctimer_new_channel()
200 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_sctimer_pwm_get_cycles_per_sec()
259 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dpwm_rcar.c55 const struct device *clock_dev; member
231 ret = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->mod_clk); in pwm_rcar_init()
236 ret = clock_control_get_rate(config->clock_dev, (clock_control_subsys_t)&config->core_clk, in pwm_rcar_init()
257 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-Core-3.7.0/drivers/i2c/
Di2c_rv32m1_lpi2c.c27 const struct device *clock_dev; member
86 err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clk_freq); in rv32m1_lpi2c_configure()
218 if (!device_is_ready(config->clock_dev)) { in rv32m1_lpi2c_init()
223 err = clock_control_on(config->clock_dev, config->clock_subsys); in rv32m1_lpi2c_init()
229 err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clk_freq); in rv32m1_lpi2c_init()
269 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)), \
/Zephyr-Core-3.7.0/drivers/watchdog/
Dwdt_mcux_wdog.c23 const struct device *clock_dev; member
82 if (!device_is_ready(config->clock_dev)) { in mcux_wdog_install_timeout()
87 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_wdog_install_timeout()
170 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
Dwdt_esp32.c50 const struct device *clock_dev; member
160 if (!device_is_ready(config->clock_dev)) { in wdt_esp32_init()
165 clock_control_on(config->clock_dev, config->clock_subsys); in wdt_esp32_init()
194 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
Dxt_wdt_esp32.c42 const struct device *clock_dev; member
108 clock_control_configure(cfg->clock_dev, in esp32_xt_wdt_isr()
152 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
Dwdt_mcux_wdog32.c28 const struct device *clock_dev; member
97 if (!device_is_ready(config->clock_dev)) { in mcux_wdog32_install_timeout()
102 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_wdog32_install_timeout()
198 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
/Zephyr-Core-3.7.0/drivers/interrupt_controller/
Dintc_rv32m1_intmux.c44 const struct device *clock_dev; member
147 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
158 if (!device_is_ready(config->clock_dev)) { in rv32m1_intmux_init()
163 clock_control_on(config->clock_dev, config->clock_subsys); in rv32m1_intmux_init()
/Zephyr-Core-3.7.0/drivers/can/
Dcan_mcux_mcan.c27 const struct device *clock_dev; member
80 return clock_control_get_rate(mcux_config->clock_dev, mcux_config->clock_subsys, in mcux_mcan_get_core_clock()
91 if (!device_is_ready(mcux_config->clock_dev)) { in mcux_mcan_init()
111 err = clock_control_on(mcux_config->clock_dev, mcux_config->clock_subsys); in mcux_mcan_init()
207 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dcan_esp32_twai.c71 const struct device *clock_dev; member
170 if (!device_is_ready(twai_config->clock_dev)) { in can_esp32_twai_init()
181 err = clock_control_on(twai_config->clock_dev, twai_config->clock_subsys); in can_esp32_twai_init()
271 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)), \
/Zephyr-Core-3.7.0/drivers/serial/
Dserial_esp32_usb.c43 const struct device *clock_dev; member
104 if (!device_is_ready(config->clock_dev)) { in serial_esp32_usb_init()
108 int ret = clock_control_on(config->clock_dev, config->clock_subsys); in serial_esp32_usb_init()
270 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
Duart_mcux_iuart.c19 const struct device *clock_dev; member
232 if (!device_is_ready(config->clock_dev)) { in mcux_iuart_init()
236 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_iuart_init()
246 clock_control_on(config->clock_dev, config->clock_subsys); in mcux_iuart_init()
265 clock_control_off(config->clock_dev, config->clock_subsys); in mcux_iuart_init()
329 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-Core-3.7.0/drivers/mdio/
Dmdio_nxp_s32_gmac.c29 const struct device *clock_dev; member
124 if (!device_is_ready(cfg->clock_dev)) { in mdio_nxp_s32_init()
129 if (clock_control_get_rate(cfg->clock_dev, cfg->clock_subsys, &data->clock_freq)) { in mdio_nxp_s32_init()
165 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-Core-3.7.0/drivers/gpio/
Dgpio_rv32m1.c28 const struct device *clock_dev; member
275 if (config->clock_dev) { in gpio_rv32m1_init()
276 if (!device_is_ready(config->clock_dev)) { in gpio_rv32m1_init()
280 ret = clock_control_on(config->clock_dev, config->clock_subsys); in gpio_rv32m1_init()
318 .clock_dev = INST_DT_CLK_CTRL_DEV(n), \
/Zephyr-Core-3.7.0/drivers/counter/
Dcounter_nxp_s32_sys_timer.c36 const struct device *clock_dev; member
150 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate)) { in nxp_s32_sys_timer_get_frequency()
166 if (!device_is_ready(config->clock_dev)) { in nxp_s32_sys_timer_init()
171 err = clock_control_on(config->clock_dev, config->clock_subsys); in nxp_s32_sys_timer_init()
266 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dcounter_mcux_tpm.c26 const struct device *clock_dev; member
220 if (!device_is_ready(config->clock_dev)) {
225 if (clock_control_on(config->clock_dev, config->clock_subsys)) {
230 if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
268 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
Dcounter_mcux_gpt.c28 const struct device *clock_dev; member
189 if (!device_is_ready(config->clock_dev)) { in mcux_gpt_init()
194 if (clock_control_get_rate(config->clock_dev, config->clock_subsys, in mcux_gpt_init()
232 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
/Zephyr-Core-3.7.0/drivers/ptp_clock/
Dptp_clock_nxp_enet.c25 const struct device *clock_dev; member
103 (void) clock_control_get_rate(config->clock_dev, config->clock_subsys, in ptp_clock_nxp_enet_rate_adjust()
166 (void) clock_control_get_rate(config->clock_dev, config->clock_subsys, in nxp_enet_ptp_clock_callback()
253 .clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \

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